The Data General microNOVA

The DG NOVA is an interesting story in and of itself, designed by some DEC expats as a straightforward extension of PDP-8 style technologies into a 16-bit minicomputer, but a couple of days ago I learned something quite interesting about its LSI microprocessor implementation, the microNOVA. For more information on the NOVA, there are previous threads on this forum here and here.

I was reading the book Minicomputer and Microprocessor Interfacing, by John Cluley (1982), and it mentioned the DG microNOVA. I was aware that it existed, and that it was an implementation of the DG NOVA much like the LSI-11 was an implementation of the DEC PDP-11, but it had an intriguing description of its architecture. It said that the microNOVA, in order to fit a standard 40-pin package, had a 16 MHz serial I/O bus!

DGCmN602E

Some digging turned up more information on this. (There’s a good page on the microNOVA on CPUSHACK, for example.) It turns out that the external I/O interface was actually two pins sending 8 serial bits each, in parallel!

The book does mention that the complexity of interfacing this bus was high enough that it was used only by the CPU and special transceiver circuits (I believe the mN603 I/O controller, from this publication from Data General) on the motherboard or backplane, which converted the serial bus to a parallel bus for consumption by external I/O devices — possibly using the same format as the larger NOVA minicomputers.

What an interesting design choice, and particularly for 1976. Even many keyboards were not yet serial in 1976! (Of course, terminal units and teleprinters were.)

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Oddly enough, only today I learnt that the TMS9900, also a 16 bit MPU, has a serial I/O bus. In some sense it’s a bit-addressable space, and the address bus is involved as well as the the 3 special pins, but the databus isn’t. I can’t say I fully understand the design choice or the capabilities.

A significant advantage of the 9900/9901 parallel I/O interface through the CRU is the ability to transfer fields of from 1 to 16 bits of data as inputs or outputs under the command of one instruction and to modify this structure from instruction to instruction. Additionally, use of the CRU allows implementation of multiple functions in the TMS9901 [Programmable Systems Interface]

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And, in turn, so did I! It looks from the literature like maybe this is a bus for explicit shift-register-style interaction, and that a number of TMS99xx line I/O expanders used it? I’ve had it on my TODO to start collecting up the parts to build a TMS9900 computer the way it should have been built (unlike the TI 99/4 and 99/4A effort, of which I have an example), perhaps I should accelerate that timeline. I’ll move it up to 2043. :wink:

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I have a TI99/4A, but also borrowed a real TMS9900 based computer for a month: the Fluke 1722A instrument controller. The difference in performance was such that it was hard to believe both used the same processor.

I never had the expanded memory for the TI99/4A. Though that would still be 8 bits (I think) at least the processor would access it directly instead of through the 9918. That should have made things faster but I never saw anybody mention that.

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It was 8-bit attached, and I think it did have better performance than the memory accessed through the VDP, but like the Commodore line prior to the thorough establishment of the C64, most programs didn’t utilize the extra memory (or didn’t utilize it well). Relying on the presence of bus-attached RAM meant that programs could only run on expanded systems, which reduced their market share.

We discussed some details of some 9900 based micros over on this thread:

Geneve 9640 - the “other” TMS9900 based micro

which includes a link to this page about the internals of the TI99/4A. It was a surprise and delight to me, but not conducive to high performance.

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Garth Wilson on 6502.org has a circuit using the 6522 serial I/O to support an N bit I/O bus: http://wilsonminesco.com/6502primer/potpourri.html#22_SR_OUT

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