The TMS 9900 processor has been mentioned once or twice or even more times on this forum. It is most well-known for appearing in the ill-fated TI 99/4 and 99/4A line of computers, which arrived a little too late and at a little too steep a price tag to compete in the market, and had a rather unusual and unfortunate architectural design, but nevertheless sold by the millions (and is therefore readily available on the second hand market for very reasonable prices). However, this machine arguably does not do the TMS 9900 justice, came along rather late in the TMS 9900’s life, and doesn’t really represent what it is or what it is capable of.
The TMS 9900 was introduced in 1976 with a 16-bit word at a clock speed of 3 MHz, making it a reasonably good performer and beating most of the first crop of 16-bit processors (with the notable exception of the DEC LSI-11) to market by a couple of years. The 8086 would follow in 1978 and the Motorola 68000 in 1979, in particular. However, unlike these other machines, the TMS 9900 was limited to a 16-bit (really, 15-bit; more on this later) external address bus and, like the 68000, had no built-in memory management. This limited it to 64 kB of addressable RAM.
Architecturally, the TMS 9900 is a true 16-bit design in the CISC tradition with an expressive set of addressing modes a la the PDP-11 (including an auto-increment, but no auto-decrement, and without the double-indirect modes of the PDP-11). In fact, if you squint a little bit at the instruction set, it kind of looks like the PDP-11 instruction set reimagined as a hexadecimal, rather than octal, system — there are four bits of registers (R0 through R15), rather than three, and two bits of addressing mode, rather than three. This is probably unsurprising, as the TMS 9900 has its roots in a minicomputer contemporary with the PDP-11, the TI-990. It has 16-bit registers and 16-bit external address and data buses. The instruction set includes hardware multiply and divide routines as well as an unusually robust array of bitwise operations. It does not have either floating point operations or wide register support for storing floating point representations.
(TI-990 operator’s panel, photograph by Davepitts on English Wikipedia.)
The mainframe and minicomputer world has enjoyed a great diversity of architectural decisions compared to the microcomputer market, and the TMS 9900 architecture diverges from other, familiar microprocessors rather rapidly due to its minicomputer provenance. For example, the TMS 9900 CPU itself has only three user-visible registers: the program counter, a “workspace pointer”, and a status register. There are no general-purpose registers, no accumulator, no index registers, etc.! Instead, the workspace pointer (WP) contains a memory address that represents the location of the general purpose register file. R0 is located at the address stored in the WP, R1 is at WP + 1 word, etc.. The architecture provides sixteen general purpose registers, which are located in main memory and can be placed anywhere in the address space. The processor documentation plays this up as a boon for multitasking, as the entire processor context can be changed as easily as easily as loading a new workspace pointer. Indeed, a pair of instructions is provided to simultaneously jump to a new location (or return from an old location) and update the processor’s workspace pointer.
The disadvantage of this register storage in main system memory is that many instructions require a comparatively large number of memory accesses compared to other register-rich processors, and in this respect it behaves somewhat more like an accumulator-based architecture. The simple register increment instruction INC, for example, requires three memory accesses: instruction fetch, register fetch, and register store. As expected, most instructions take a comparatively large number of clock cycles to complete due to this and other architectural decisions; the fastest instructions (such as branch unconditional and many of the single-operand instructions) take 8-10 clock cycles, or longer if more complicated addressing modes are in use. The slowest non-division instructions can take well over 60 clock cycles, and division may require as many as 124 clock cycles plus overhead for addressing modes!
Another oddity for a microprocessor is that it is a true word-addressed machine. Whereas most early 16-bit microprocessors (and indeed many minicomputers, such as the PDP-11) could directly address memory on a byte level, the TMS 9900 cannot. It has only a 15-bit external address bus, and unlike other true 16-bit processors like the LSI-11 or Motorola 68000, it has no external signal to indicate byte operations or to communicate even or odd addresses; all address accesses are to even addresses.
This is probably due in part to the next interesting departure from other architectures of our time: the TMS 9900 neither has an I/O space on its address bus to allow I/O transfers over the same data lines as memory (like the 8086) nor uses exclusively memory-mapped I/O (like the LSI-11). Instead, it has a strange (by modern standards) serial I/O bus in addition to the parallel memory bus. This address bus is bit-addressed, and exposes 4096 bits of I/O space which can be transferred in 1- to 16-bit fields of any included size. Since I/O can be performed on any arbitrary bit boundary, memory bus addresses have no need of bytes! An internal “Communications Register Unit” (CRU) manages this serial communication, and TI marketed a family of CRU I/O devices for the 9900 family of processors, including the TMS 9901 parallel I/O and interrupt controller, the TMS 9902 asynchronous serial communication interface, and the TMS 9903 synchronous serial communication interface.
The processor documentation spends some time discussing the CRU and its usage for I/O, including providing several helpful diagrams for creating CRU-attached I/O interfaces out of discrete logic, such as this multi-bit parallel I/O device:
An oddity of the documentation for this system, and indeed for many of TI’s designs, is that the bits are numbered “backward” from most other systems. A0 and D0 are the most-significant address and data bits, respectively, while A14 and D15 are the least-significant bits. This poses a real hazard for the system designer, as frequently pin names will mismatch between chips that are being interfaced from other manufacturers, with D0 on the TI connecting to D15 on an external device! This becomes even more confusing when the serial communication documentation for CRU devices comes into the mix, particularly if one is used to more traditionally numbered systems.
The chip’s minicomputer roots and its designers’ vision for multitasking also comes into focus in its support for interrupts and system traps. It exposes 16 hardware interrupts and 16 software traps, each associated with a code entry point and a workspace pointer to store context. Note that where another machine might associate an interrupt with a code location and a stack pointer or processor status word, the 9900’s memory-backed register architecture allows it to associate it with a fresh set of registers!
The electrical care and feeding of the original 9900 is simultaneously complicated and difficult, and pleasant and straightforward, depending on which part of the design you are looking at. It uses a large 64-pin package, which means that no bus multiplexing is necessary, and the address and data bus lines are neatly arranged in sequential order down opposite sides of the chip, with none of the scrambled pin layouts that often plague smaller packages. However, being an NMOS package with a complicated external clock, it requires three operating voltages (5 V logic as well as low-current -5 V for the NMOS substrate bias 12 V for (presumably) clocking circuits) and a four-phase non-overlapping clock 12 V nominal clock signal with 75 mA of drive current. TI helpfully provides a companion clock generator chip which takes an input clock (or crystal oscillator) at 4x the 9900 clock frequency and provides the requisite signals — while drawing about 500 mA!
Later chips in the TMS 9900 family, such as the TMS 9980 and TMS 9995, did away with many of these electrical complexities (such as requiring only a TTL-level single-phase clock or a simple crystal, a single voltage, and a 40-pin footprint) in return for other difficulties such as multiplexed pins and an external 8-bit data bus.
The TMS 9900 gets a bad rap due to the market failure of the TI 99/4A and the relative unpopularity of its minicomputer cousins compared to the DEC, Data General, and other contemporary offerings, as well as relatively poor performance compared to other 16-bit CPUs. However, considering its relatively early release date of 1976 and the uniqueness of the architecture, it seems to be an interesting sidebar in processor development worthy of the study of a retrocomputing aficionado.
Bitsavers has documentation on the TI-990 series of minicomputers as well as the TMS 9900 and support chips. The data sheets for the 9900 family of chips are somewhat confusing and incomplete without reference to the other user manuals and TI-990 documentation.