I want a prgramable device with 5 volt I/O, a PLCC package and
Open source programming. I want to connect it my way, not fight
the software to fit things in. I have really bad luck with routing and race
conditions, some times it works and some times you need to wait a day or too for the version of software I have. Upgrading is not a option,
Also I like using AHDL, other wise I have to use ( rather rude view of) VHDL or VERLOG. Why not a real RTL languge, they had them with
puch cards.
The goal is 384 LEās, not really what you use. I got a spare
DE0 floating around, and might use that. Serial memory internal or external.
Does the LEās used include I/O logic for devices?
I have been reading up on the LGP-30 and itās cheaper, transistorised brother the LGP-21.
The instruction set is very reminiscent iof EDSAC, single upper-case character instructions, with a strong mnemonic value.
The LGP-30 was clearly designed around the quirks and limitations of the magnetic drum memory - an approach which is commonplace with every machine design - designed around the requirements of the memory sub-system.
However, by all accounts it was an awkward machine to program as a result of having to optimise the program to the motion of the drum.
It might be an inspiration for a bit serial design, but simplified to use conventional serial SPI memory.
It could be any of the industry standard 8-pin SPI memories. Flash, RAM or FRAM.
These serial memories share a common pin-out and a common set of commands.
I like FRAM, because of its non-volatility, and I was proposing using an Arduino initially as the serial programming interface for this minimal machine.
(Highly parenthetical, but Iām reminded of Shane Goughās TGL-6502, which uses an 8-pin ARM chip to emulate a 6502. So, in this case, perhaps the awkward to program drum machines could run an emulator of a more regular machine.)
(Edit: I now realise this is also the approach taken by the Gigatron)
I read that the characterisation has not shown any finite life. The lifetimes are āat leastā and not āon averageā and they havenāt seen failures. (Please correct me if Iām wrong about this.)
AFAICT thereās no reason to avoid FRAM on the basis of lifetime.
Still read the fine print for writes Core memory (1970) is about 10^10 cycles read/write
an hour.(.75us). Modern machines do that in a second.
The nonvoiltile memory was to hold
small ROM programs or tables or be safe from a power fail
or distruction of the universe. The fact that many machines of
that era saved a subroutine address at the start of subroutine
prevented rom being used had been avaible.
Since my TTL computer design saves the return address @ sp + 0
I plan to use EEPROMās for a 4K BIOS at the top end of memory.
(IO is at the very top). I still can patch the bios if need be later.
FRAM would be nice but not needed.
I got a free āFRAM for Dummiesā from Texas Instruments a few years ago, and as I recall the booklet said that wearing out the FRAM was the one thing you didnāt have to worry about. Iāll have to go to the man cave to see if I can dig out the booklet again.