One Page Computing

BTW Ken, good idea for a challenge. I see you mused about bit serial CPUs over here:
AnyCPU - Bit Serial CPUs

@EdS,

Yes - I have found another itch to scratch.

I found a couple of papers this afternoon describing two contrasting bit serial machines - both based on a subset of MIPS-IV instruction set

It turns out that a 2-bit ALU can be more than twice as efficient as a 1-bit ALU, and it also reduces the hardware complexity of the rest of the machine.

2-bit “Ultrasmall”

1-bit “Supersmall”

It may transpire that a 4-bit serial ALU provides an even more efficient implementation - depending on the resources of the particular FPGA.

Meanwhile I am still looking at a traditional TTL implementation of the bit serial cpu. The 16 x 4 bit static RAM (74F219) makes an efficient way of implementing four 16-bit shift registers.

Dispensing with conventional parallel RAM and ROM, and using Microchip 8-pin SPI non-volatile SRAM as a replacement, can lead to savings of 8 or 10 devices.

Microchip NV RAM: https://www.mouser.co.uk/datasheet/2/268/20006008C-1826938.pdf

Compared to the 38 IC Gigatron, it looks like a 16-bit, 64K bit serial machine could be implemented in 10 to 20 TTL packages with an instruction execution frequency of perhaps 4 to 5 MHz.

I am currently reviewing the “Suite-16” instruction set and architecture to see whether it might be a viable candidate for bit-serial implementation, with a 75% reduction in the hardware chip-count.

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Flags and interupts and conditonal logic will add about 4 chips for each function, for TTL logic, if you have them. It is more the case of XOR gate
here, a AOI there, one J/K FF else where, than complex logic.
Ben,

4 bits is indeed a sweet spot. The original Nova was 4 clocks x 4 bits, as was my dietST attempt to fit a Smalltalk processor into a Spartan 2 15 (96 CLBs x 4 = 384 LUT4s and flipflops plus 2KB of BlockRAM).

The only thing that is more complicated in a 4 bit data-path compared to a 1 bit one is handling shifts and rotates.

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