What is AND-OR logic?

I found the term “AND-OR” on page 357 of the VR4300 user’s manual. Does anyone know the truth table or schematic?


On second thought, the AND-OR block probably consists of 8 AND gates, each of which takes one input from the status register and the other input from the cause register. Then all 8 AND outputs are probably fed into an OR gate.

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This is how I’m reading this, as well.

But the way this is used in the manual makes me also curious: is this an established term?
(This is on page 357, section 14.5.2 Masking of Interrupt Request Signals.)
Sadly, given the current state of web search, trying to search the term (verbatim or not) is a rather futile endeavor.

New term for me. The fiddly little bits your mother never told you about.
See also chapter 6. for irq priority.
I can see why retro cpu’s are back. Very simple to use
compared to the mammoth software over head of todays RISC.

There’s a particular transistor structure which is quite efficient, see perhaps

Think of these two-level gates as the next kind of gate beyond the simple NAND and NOR. (Logic gates are by default inverting, in a lot of technologies)

I think that block is named wrong, it is the priority encoding for the irq’s, not
just a simple AOI logic.

maybe they put another inverter at the output and it’s cancelling out the AOI inverter?

Once upon a time I wrote a 32-bit VM in assembler on a retro 8/16 bit CPU. It assembles to a shade under 16KB.

Some time later, I re-wrote it in RISC-V and it’s 10KB. Not sure where the overhead is there… It also took me a few days of spare time for the RISC-V version and weeks/months for the 65C816 version.


I tend to think of simple machines, 8 bit cpu, some rom, some ram, a uart or two and
8" floppies, and a 4K OS. I need to boot strap from bare metal err silicon, so can’t spend
large amount time working on hardware I bairly understand, or unable to buy or build.
The PDP 8/e and the IBM 1130 were both computers I got to play with, so I think small
for operating sytems, with no VIRTUAL memory and flat memory access.

A 650 page pdf for the VR4300 is just too much information to process all at once,
so I have to assume it is a complex software design for the OS.

What boards are you using?
Retro to me is any computer before the IBM PC, or creative design like Acorn Archimedes
or the AT&T Hobbit. I use to like FORTH untill I found you really don’t have Disk I/O
to load and save programs and data.


This is for Nintendo 64. I’m working on creating hyperlinked documentation that contains the same information as the manual. That way it will be easier to navigate and more people will be able to learn it. You can find it on my GitHub as I write it.

My own design 6502/65816 board with 512KB of RAM as well as a few other old and new 6502 systems. The RISC-V “board” is the same board running an RV emulator written in BCPL although I do have a ‘real’ RISC-V board or 2 - the ESP-C3 which has ~400KB of RAM.


Not sure I’d agree with you there. IF it had priority encoding then the document would mention it. Further more, by doing the ‘priority’ thing in the CPU then the user/software designer gets to decide what the priority actually is. Although the priority is quite likely to be IP7 as the highest to IP0 being the lowest, it isn’t guaranteed IMHO.

See Programmable logic array - Wikipedia for a fuller description of AND-OR logic and the classic programmable devices that implemented it and made it available to designers.

Think about a problem like: I want RAM enabled for these three disjoint address ranges, I want ROM enabled for these two disjoint address ranges, and I want the data-bus buffers enabled for RAM and ROM (but not IO)" This would be stuff like ‘RAM = (A8 high AND A9 low AND A10 high) OR (A15 high AND A14 low)’ etc.

Maybe you can check sources of a N64 emulator?