PiGP-30, a Raspberry Pi base LGP-30 emulator


After some discussion with Oscar, the creator of the PiDP-8 and PiDP-11, I decided to try my hand at creating a functioning LGP-30 emulator along the same lines.

Some preliminary information about this emulator is available at https://curuvar.com/pigp30

I am planning on making this available in kit form (or perhaps as an assembled unit) and would be interested in gauging the desire for such a kit.


But will it run Mels Blackjack program?



It does run the BlackJack program.

1 Like

For those not so familiar with the LGP-30, I once wrote a blog post in the honor of it:

1 Like

This looks pretty cool. I sent in a tip about this to Hack-A-Day, I hope that it is OK.

Very interesting! I think I found it before, but never realized that there’s the Key 1 missing and using a lowercase L instead. Great idea.

You know about the LGP30 emulation that’s part of the Open SIMH project, right?

I’m amazed how minimal that is, there’s not even room for a word of data in the flip flops, and barely room for an address (not sure if they are ever used for that)

I was thinking about how you could have an analogous memory subsystem using current RAM or similar, that lets the rest of the computer be so simple.

Here’s what I came up with:
You have a 5 bit counter, which for counting from bit 0 to bit 31 of the words. This is analogous to part of the rotation of the drum.

You use a 32 byte SRAM chip - 5 address lines, 8 data lines, and reinterpret that as 8 tracks of 32 bits each. Each register is on a separate track: Accumulator, Operand, Program Counter, and there’s room for 5 more tracks if needed, for registers or timing signals. The address lines are connected to the 5 bit counter.

You use a second of these register SRAM chips so you have one for reading, one for writing, and alternate which one you are reading and which you are writing every word (32 bits). In general, you copy the data from one to the other, except when there’s a deliberate change to make. So you’re always writing the new state of the registers to the next chip.

For the main RAM, you only want one data line, so you’re reading/writing one bit at a time. There should be 5 address lines to select a bit within a word, and 12 to select one of 4096 words, so 17 address lines, for a 128 kbit chip.
The 5 lower address lines here are also connected to the same 5 bit counter as the register memory. The other 12 address lines are connected to a serial-in, parallel out register chip - the idea is that the control system can copy from one of the registers to these 12 address lines when needed.

You might want try using modern magnetic memory for main menory later.

Maybe interesting:
Regarding switching memory images, somewhat related was the fast drum memory invented by Ed Fredkin and designed by Gordon Bell for the DEC PDP-1, which was used for the timesharing systems at BBN and MIT. The PDP-1 used core memory, which requires a (re)write cycle to write the data back after read, since read is destructive. Switching users was implemented by having the drum precisely synchronized with the memory and letting the CPU read all addresses. The signal read would be written to one track, while the rewrite signal was intercepted, using the data from another track to restore the memory contents – which enabled user switching with zero latency, besides the time required to cycle over the 4K memory. Quite ingenious…
(It may be more than a coincidence that Ed Fredkin first wanted to start a business on the LGP-30, before he fell in love with the PDP-1 and joined BBN. It’s very likely that he had thoroughly studied the LGP-30 architecture.)

1 Like