Lost web page - PDP 2

Found a web page for the PDP 2. A what if project.

For a bit of background:
The PDP-1 had been initially announced (in the November/December1959 issue of Datamation) to come in three versions: 18-bit, 24-bit and 36-bit. As we probably all know, only the 18-bit version was ever released. However, the PDP-2 tag name was reserved for a future 24-bit version, which never emerged. Instead, there was an obscure version of two PDP-1s tied together, with two machines in total (as far as we know), specially built for and partly by a US Intellegence Agency.

There was an obscure version of two PDP-1s tied together, with two machines in total (as far as we know), specially built for and partly by a US Intellegence Agency.

Top secret spy stuff, I guess.

It’s so secret that I got it, in fact, mixed up with the PDP-3.
The PDP-3 was the reserved designation for the never-built 36-bit version of the PDP-1, and if we multiply a PDP-1 bx 2, we do get 36-bit.

Gordon Bell is quoted here:

“DEC also never built a PDP-3, although one was designed on paper as a 36-bit machine. […] In 1960 a customer (Scientific Engineering Institute, Waltham, Massachusetts) built a PDP-3. It was later dismantled and given to M.I.T.: as of 1974, it was up and running in Oregon.”

Scientific Engineering Institute was, of courses, founded by the CIA and has been said to be their very source of special equipment of various nature.
(There’s more on this, detailing that it was actually built by S.E.I., and this quite secretively. Nothing seems to be known about what it had been used for. – I can’t think of the source at the moment.)

I suspect many of the early computer companies, played some part in the Cold war era,
that the public did not know about, both in the US and the UK.

There was a computer called CASINO. There is a rumor that it was built out of discarded modules there were used for the PDP-2 prototype. So that information is in conflict with the PDP-2 never being built at all.


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This lists all PDP models, real or not, that I have heard about:

Scientific Engineering Institute built the previously mentioned CASINO computer, having a memory that “consists of two PDP-1 memories placed on top of one another to provide 38-bit words.” That sounds pretty close to the PDP-3, especially if you are willing to believe there are two parity bits, and Noel Chiappa thinks they are one and the same. Talk:CASINO - Computer History Wiki

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As far as I know, DEC was known for never doing parity bits.
A PDP-1 memory block is definitely 18-bit and 4K (but there was also a 1K memory, which went initially with the BBN prototype machine – which is, where Ed Fredkin’s FRAP assembler comes into the picture – and then apparently had a journey through various installations). So 38-bit memory would have been somewhat difficult, unless you installed a third block just for the parity bits.

I’m quite relieved to read:

PDP-5 12 First minicomputer

We’ve become used to reading about the PDP-1 as the “first minicomputer”. However, the PDP-4/5 were a deliberately downgraded architecture to meet a certain demand, which had been mostly ignored before, which lead, with the redesign for chip cards, to the PDP-8, which was first praised under this term. Moreover, the PDP-1 was roughly comparable to the IBM 1401, which was announced also in 1959, in computational power and memory size and generational design and featured a rather overbuilt I/O section – and I’ve certainly never heard of the “IBM 1401 minicomputer”.

I think marketketing at the time made a big impact. IBM rented equipment, so you never
had the surplus of older computers like DEC as all the out dated stuff was removed from use.
That says why more people have heard about DEC, and terms like ‘first’ came because people with new ideas got to use them.
Where would UXIX be today if developed on a IBM-1130 ignoring the fact UNIX uses 8 bit bytes?

I think it’s futile to try to identify the first minicomputer (and often, the first of anything) since people tend to disagree about the exact definitions. This is exacerbated by how the term might be defined in a historical context, i.e. a 1960 minicomputer isn’t the same as a 1970 minicomputer. I believe the term was first used for the PDP-8. It probably makes sense to retroactively apply it to the PDP-5. I can see how a similar argument could be made for the PDP-1. I think we’ll have to just accept people using the term somewhat loosely.

I try to correct people who are way out of line, e.g. calling the PDP-10 a mini, or the PDP-11 a mainframe. That happens, and it’s not ok.

How about that extra 19th plane? http://www.bitsavers.org/pdf/dec/pdp1/F17_PDP1Maint.pdf#page=214

For the benefit of readers, there is a note in the PDP-1 Maintenance Manual, reading,

NOTE; The core bank actual!y includes an extra core plane which
is completely wired in. There are therefore 19 planes and 19 inhibit
and sense windings. The extra 19th plane is not ordinarily used, but
is provided in case it is wanted for some special application. The
following discussion treats only the 18 core planes that are ordinarily

This is actually interesting – and I had totally overlooked this. There are provisions for parity, but it isn’t used and there is no provision for this on the memory bus (as far as I would know). Maybe, a “government-use wildcard”?

(To me, it always appears to be important in this context that the PDP-1 was originally announced in 18-bit, 24-bit and 36-bit variants, which were later split into the PDP-1, PDP-2 and PDP-3 designations, – and then only the low-cost variant was ever built, as well as drastically reduced derivatives of the architecture, as in the PDP-4/5. Which somewhat describes the path DEC would take: amazing, MIT-like capabilities, which were still affordable, but this came also at a price in terms of what it took to keep costs low, as DEC eventually determined what its very biotope in the bigger market may be.
But it’s also surprising in this context that there would be this spare plane, completely wired, just in case, but never used. This may also illustrate that, while memory was prohibitively expensive, the real cost factor was seen in the number of registers and bits per register. So, having that spare memory plane wasn’t as ruinous as actually wiring it up with all the logic involved.)

In another place, @larsbrinkhoff noted

Seymour Cray is credited with the quote “parity is for farmers”. As a PDP-10 fan, I’d like to think he’d say the same thing about byte addressing. Cray later changed his mind and added error correction, quipping “more farmers have computers now”.

(I’d remembered the first quote but wondered if it was from the house of DEC)

This is absolutely not true on the PDP-11, two signals on the 16-bit Unibus backplane are dedicated to parity error detection, and two extra data bits are carried on the Modified Unibus backplane (used for memory devices), one parity bit for each byte on the bus. Parity could either be computed on the memory board itself, or on an external parity controller that fitted to the Unibus. The MS11-L MOS memories had one bit per byte and checked parity on-board (see EK-MS11L-TM-001, MS-11L MOS Memory Technical Manual, p. 3-26), but some other memory boards simply transported the parity bits to the Modified Unibus slot and had their parity computed by, e.g., an M7850 parity controller.

It’s true, Unibus had dedicated parity lines on PA and PB, but this was also 10 years later.
(I actually had a quote in mind, but I couldn’t find the source.)

The PDP-8 had optional parity, as well, compare the Type 188 Memory Parity module.

What about parity on the ALU logic? Did any one use that after the 1960’s,

Well, there was that whole industry segment of “fault tolerant” transaction machines, of which the best known was Tandem, but there was also a company called Stratus and maybe others. They didn’t just have parity, they ran two or more entire CPUs that checked each other on everything. They had promotional material that showed someone running a paper clip over the backplane while the system was running, etc.

With the extremely small transistor sizes we’re getting to now, it wouldn’t surprise me if the manufacturers were doing this sort of thing again in the last few years. But they wouldn’t want to talk about it because it would just scare the customer base.

Notably, this is also what UNIVAC did: the UNIVAC I had two ALUs, two bus systems, two everything – but, somewhat contrary to this thread, just a single mercury delay memory. (However, there was parity and excess-3 representation.)

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NEC had machines that took parity error checking through the ALUs without replicating them. E.g. parity of input parits == parity of carries ^ sum, or Parity of an AND ^parity of OR, parity SHL ^ parity of SHR