You really shouldn’t ask me things like this! 
However, here you are:
An important thing to know about the PDP-1 is that it is in it’s essence a commerialized Whirlwind or TX-0 built from transistors-only modules (which had been until then DEC’s bread and butter). There are some architectural differences, like the TX-0 (originating from a test design) has just a 2-bit instruction set and relies heavily on micro-coded instructions, the layout of which varied over time, while the PDP-1 has a 5-bit instruction set (+1 indirection/reverse of condition bit) with additional micro-coded instruction groups (in the 12 address bits). However, all of them followed a distinctive line of realtime computers with a display and sense switches developed at MIT (and DEC’s founders had worked at these projects), and there are considerable similarities in TX-0 instructions and the PDP-1 instruction set, regardless of the differences.
(Another way of looking at this is as a tiny SAGE system in box. Indeed, rumor has it that the reason why DEC developed the PDP-1 in just a 3 and-a-half months effort and announced it in 1959, prematurely to its business plan, was because there were rumors that the Air Force would be looking for such a system for localized missile control. However, I haven’t found any source corroborating this. So this is not a narrative recommended to the serious student. 
)
Having said that, the configuration was the first actual production model and had a standard block of 4K 18-bit core memory, a built-in paper tape reader and a separate paper tape punch (also built-in), and a Type 30 CRT display and a light pen.
(More precisely, it was a PDP-1C, as opposed to the production prototypes PDP-1B at BBN and LLNL, and the later timesharing version PDP-1D, which was designed to BBN specifications. For a bit of Internet folklore, the PDP-1D prototype at BBN was eventually used to write and cross-compile the code for the IMPs and was probably the first computer to distribute software updates over the network, as it came online on the ARPANet.)
The machine in question (the “RLE PDP-1”) arrived in fall of 1961 (when that port effort took place), the display only at the end of the year.
Technically, the memory cycle time was 200Hz (or kilo-cycles) and each instruction was 1 memory cycle (5 microseconds), adding an extra cycle, if there was memory access, and another one for each step of indirection. Memory came of blocks of 4K of core memory, expandable in further banks of 4K to up to 64K.
The first few machines didn’t have instructions for multiply and divide, but dedicated shift-step instructions for partial one-bit operations. Eventually, there was a hardware multiply/divide module and machines seem to have come in this configuration as soon as 1962, while older ones were upgraded.
Finally, here’s a link to the basic instruction list.
Not covered here is that the PDP-1 has a rather sophisticated I/O section with direct memory access and asynchronous I/O, an I/O mixer, and a sequence break (interrupt) section, which may account for the better part of the hardware.
(There had been plans for a 24-bit version PDP-2 and a 36-bit PDP-3, which were also mentioned in the 1959 Datamation announcement, but nothing became of those. That is, a single PDP-3 was actually built by SEI and used to process radar cross section data for the Lockheed A-12. This one featured already hardware multiply/divide in 1960, as well as 511 auto-index registers, as seen later on the PDP-8, the memory access time was doubled, though. — SEI is actually CIA’s Scientific Engineering Institute and DEC handing over plans to the CIA, in order to built the machine on their own, must have been quite a show, provided Ken Olsen’s ramblings on government contracts.)
