So I noticed the 44 pin versions of the W65C816S have two internal logic ground (VSS) pins right in-between address pins 11 and 12. You can see this on pages 10 and 11 on the datasheet.
Surely they must have had a reason, right? Does it make it easier to ground everything in the chip, like with less distance to all the components, putting them in the middle like this?
There’s also a not connected pin in-between A1 and A2.
(There can be strange pin numberings sometimes, see this writeup on the Z80 although it’s not address pins this time: Why the Z-80's data pins are scrambled)
Many early chips 1960’s had Ground and Vcc the middle.With better tech,(read less power) one could move the Gnd and Vcc to the corner pins with SSI, 24 pins and bigger it all fair game for chip layout .Now we have more vcc and gnd pins than IO it seems.Don’t forget many LSI chips had +12 and -5 back then as well.
I definitely prefer having fewer pins whenever possible and having them organized (less opportunity for mistakes) but backwards compatibility is also important, so even if WDC could remove the NC pin and combine those VSS and move them to the corner it’s probably not worth it.
Electrically, you want the output drivers to be close to ground pins, so putting grounds in the middle of the chip edge and/or in the middle of busses does make sense.
If the two pins were in two adjacent corners of the same side instead, the their total distance to other pins on that side would be the same, so I’m not sure about distance.
Node 399 is an address pin - ab11. I think the 6502 would predate this kind of consideration and optimisation. (Indeed, I think visual6502 doesn’t show power and ground, as a decluttering optimisation.)
Stands for address bus, I suppose. Closest thing to what I’m looking for I see there is two checkboxes: grounded diffusion and powered diffusion. Ain’t nothing like the real thing, I’m afraid.
Sorry, I meant to say it doesn’t show the metal layers for the power rails. As you note, it does show the diffusion areas which are directly connected to power and ground. And that’s enough to figure out the logic and function.
I think power distribution and clock distribution were not terribly difficult problems in the era of the original 6502. Discrete TTL and CMOS of course might be pressed into service into designs which are larger and run faster, and so such considerations may well apply at the board level, and at the points of connected up power and clock.
They arent really “shoved” in the middle if you think about it. On a DIP package, there is still a ground pin in between A11 and A12, it just happens to end up on the corner of the DIP package instead of the middle of a side on a PLCC package, and that’ll simply be due to how the pins arrange themselves in different packages.
(There is also another ground pin in the middle on the opposite side of a PLCC.)
So this probably just comes down to how the pads are arranged on the die and how they end up connected to the lead frame for the package they end up in. If you look at a photo of the die of a 65816 you’ll see two thick traces running around the perimeter of the chip, one for each of the two power rails. Those two rings each have two pads connected to them on opposing sides of the chip.
In a DIP package there is one VDD pin and one VSS pin grounded to these rings, but on PLCC they have more pins available and seem to have bonded more connections for power and ground (two VDD and three VSS). And yes, more connections to both power rails will be better overall for the supply within the chip. Its why modern chips tend to have so many power and ground pins (modern CPUs needs hundreds of amps at the low voltages they operate at).
As for putting two next to each other and leaving one pin NC, perhaps this comes down to how the pads of the die align with the lead frame. Maybe they had to skip a pin here and there to keep the bond wires tidy or not stretching too far. If one of those happens to fall close to a ground, why not bond it to ground? More connections to ground isnt necessarily a bad thing.
Its hard to tell from the low res photo I found of the die, but there might even be two rings for ground. Perhaps the thicker one is for the IO pads, since they need to drive more current, and there almost appears to be a thinner ring which could potentially be for the CPU core itself. Hard to say without digging further.
In a DIP package they could potentially bond both of these ground rings to the same pin in the package (since the pads on the die are directly adjacent), but in PLCC with more pins available perhaps they give each one its own pin? :shrug:
Just some thoughts. It would need some more studying of the die and the lead frame of a PLCC44 package to try and make some more sense out of it.
Some of the Z80 family of chips are limited by their ground current. Some of the older NMOS chips like the DART run close to 60C flat out, in one hot spot at their ground pins. It has to tolerate not just it’s own VCC/VDD current, but also any current it’s sinking from pull ups etc.
Modern fab processes often start out as a template for the dice and maybe the package target. These often a grid of sub dies. Each with it’s own power supply. It allows a lot more flexibility to have multiple power rails within the IC fabric. ICs may only use one block on the grid, or they may use all of them. They may all share and interconnect VDD and GND or keep them separate.
The result however is that you tend to find many VCC/VDD and many GND pins spread out over the package. This makes handling higher currents in the much more fragile modern processes more plausible.
In the early days functional pins being spread out rather than neatly in a row was just down to “logical routing” rather than “physical routing”. The pins ended up being what was easiest to route.
In modern times, those “grid block” dies can result in one block requiring more pins than it’s block has physically, so it uses another block and the interconnect fabrics to borrow pins. These pins may however be spread out in seemingly random locations on the package.
