I think, the connection to the data bus is implicit on the 6502 and the availability is only controlled by read/write status. Therefore also the write-back on read-modify-write: whatever is on the internal bus is also available on the outside, if it’s a write cycle. (Regarding the path of P during interrupts and BRK, I’m not sure. Probably the ALU?) The major difference would be that there is now a requirement to explicitely latch the data for it to become avalaible on the bus with the W65C816S.
But I do second @accelulator , it really needs a logic analyzer to confirm anything about this. (Or someone who is familiar with reading the bare silicon, like Ken Shirriff.)
It’s when there are that many 1’s and 0’s listed that I really start to appreciate more human-readable names, but that table is still pretty easy to read. That overbar to indicate “Read, not write” is a clever space saver, but I’d hesitate to say they should’ve filled the columns with R’s and W’s instead.
Writing peanut butter to the stack, on the other hand…
