Isn’t this what t1 and t5 are doing, complementing before and after the adder?
I’m not too familar with these low level aspects, but, maybe, there wasn’t any time left to add another stage, in order to complete in a single memory cycle. (The timing is rather complex, because there’s no central clock, just local timing networks, i.e., various delay lines. And this was designed from existing DEC modules, in just 3 1/2 months…)
Saving logic was important back then, that may have been more important than saving states.
Sorry for the nitpick, but LLNL usually means Lawrence Livermore National Laboratory. I have rarely seen Lincoln Laboratory shortened to anything, but the website does have LL: https://www.ll.mit.edu/
(Is it better to reply here, or on the GitHub issue page?)
Yes, my bad. Thanks for the correction.
I’m not sure what’s best, but I think I prefer a comment on the issue.