I found this site after watching a video about transputers on the Retro Bytes YouTube channel:
I thought it would be interesting to transputer fans here.
2 Likes
Nice find - and a pleasant surprise to see it’s still active as of last year.
August 2023 - Release of the PC based Inmos Transputer T800 Rev. D VBC emulator (version 1.5), release of the PC based Inmos Transputer T425 Rev. C VBC emulator (version 0.7) and release of the PC based Inmos Transputer T805 Rev. D VBC emulator (version 0.1). Also releases for macOS (64-bit). The T805 VBC emulator is new. The T800 VBC emulator has had a bug fix in the FPU to resolve a problem seen when running the savage test bench. The T425 VBC emulator and T800 VBC emulator both had bug fixes in the link engine.
(Gavin Crate was mentioned previously in the thread Transputers in space: SOHO (and others))
Some good comments on that video. Set me off on a bit of a trail…
Parallel processing using transputers or Occam (or both) (15 page pdf) by C. R. Askew, Southampton, “surveys the field of multi-transputer supercomputers, both presently available and planned. The programming language occam is described, and other languages which will soon be available for the transputer are mentioned. Programming strategies for large numbers of processors are presented.”
Several operating systems for transputer based systems are briefly described in this 200 page thesis: DISTRIX, MERCURY, TROS, VSX, QIX, SURFACEWARE, EXPRESS, TROLLIUS, MEIKOS, GENESIS, TransIDRIS, HELIOS
Trillium Operating System (3 page pdf) by Burns et al. 1988, Cornell.
Trillium is an operating system designed for a loosely coupled, message passing ensemble architccture, such as the hypercube class of machines. It has been implemented for the FF’S T-Series[1], a transputer [2] based machine. Trillium presents a uniform programming environment that extends out of the parallel processors to encompass the front end computer and and personal workstations accessible over a network. C and Fortran compilers are available along with a suite of backend development tools including a transputer board simulator.
The T series is very briefly described here, and in more detail in this Sandia document: Floating Point Systems FPS T Series (1 page tex)
The company is no longer marketing this product.
Hypercube architecture - Vector processors
Architecture: The Inmos T414 Transputer is a 32-bit CMOS processor, rated at 7.5 mips, with 2 Kbytes of on-chip RAM with one-cycle access that serves as a large register set. There are 4 links which can sustain .7 Mbytes/sec in each direction and can be multiplexed four ways to give 16 links for the maximum hypercube configuration. Aggregate external bandwidth for a single node is 5 Mbyte/sec when 4 input and 4 output channels are active simultaneously.
The Mark II version of the T Series machines (due in 1988) will use the T800 Inmos Transputer which is a 10 mips processor, with 4 Kbytes RAM and 1.7 Mbytes/sec bidirectional links. It also has a 1.5 Mflop floating-point unit.
Memory: Each node has a local memory of 1Mbyte of dual-ported RAM that will be increased to 4 Mbytes in the Mark II machine, with further upgrades to 16 Mbytes later.
Vector processor: The vector processor is a proprietary machine with its own instruction stream, which incorporates a 6-stage 8-Mflops adder and a 7-stage 8-Mflops multiplier. using the Weitek floating-point chip set with a cycle time of 125 nsec. The bandwidth to/from memory is 192 Mbytes/sec.
On the Mark II machine, the vector processor will be upgraded to an 18 Mflops (64-bit arithmetic) engine, with a bandwidth to/from memory of 320 Mbytes/sec.
Maximum number of nodes that can be connected is 2^14 (16384), giving a peak potential execution rate of 262 Gflops for 64-bit operands.
Eight nodes with one system node and disk make up a module. Two modules make up a cabinet. The maximum configuration has 1024 cabinets.
Configuration: The system is hosted by a DEC MicroVAX II which is included as an integral part of each T Series system.
A cabinet contains two system disks which the user may reference through the system node network. I/O peak transfer rate 80 Mbytes/sec for a 16-node cabinet system.
Interconnection to other systems is through an Ethernet interface on the MicroVAX although work is in progress to provide a VME bus interface.
The minimum system is a single cabinet model T 20 comprising 16 processing nodes with a maximum peak performance of 192 Mflops. It weighs around 300 lb, consumes 1.7KW, and has a footprint of 5 sq. ft, with dimensions 24.1"w x 24"d x 58"h. The largest model is a T 40000 with 1024 cabinets although the largest so far delivered is the T 200 (128 processors) at Los Alamos.
Software: The T Series runs under the ULTRIX operating system on the MicroVAX front-end. Comprehensive libraries are included …
Languages: Fortran, C, and OCCAM 2.
Performance: The T 100 can perform a matrix multiply at 596 Mflops and can solve a linear system at 135 Mflops. A quantum Monte Carlo benchmark on the T 20 at Daresbury ran only 1.7 times slower than a CRAY 1S.
This 10 page pdf describes the second generation, which uses T800 in the fabric to connect custom vector processers.