The reDIP RIOT is an open source FPGA board which combines the following in a DIP-40 size package:
Lattice iCE40UP5K FPGA
1Mbit FLASH
5V tolerant I/O
The reDIP RIOT provides an open source hardware platform for 6530 RRIOT / MOS 6532 RIOT replacements.
Looks like a really nice package , but 40 pins are kind of small. 48 pins could get you s few more address bits on the 65xxx or what ever you want .retro.
8 bit micro’s were limited with 40 pin packaging and device complexity and slow IO after the 1980’s.
I have no idea what the exact intended use of it is, but I would design high speed 8 i/o bit replacement chips
and a pipe lined memory bus for 8 bit CPU’s. Static memory today is large and fast, 25 ns access
time for 32K x 8 ram. A apple II at 10x the speed comes to mind here.
Apparently, limiting the number of pins was a relevant cost factor. E.g., it’s the entire raison d’être of the 6507 variant of the 6502, which is internally the same chip. – Does anyone know how much this actually saved in manufacturing costs (e.g., in percentages)?