An interesting video making a point on the Apple IIGS, its 65C816 processor and the related Megahertz debate:
(Also, I’m seeing a visual quote by a certain “BigEd”, where it’s about helpful forum posts.)
4 Likes
Ah, famous at last!
I didn’t realise the '816 accelerator cards had logic to detect the slow-running opcodes and adjust the clock accordingly. Ingenious!
Edit: oh, and the idea that WDC never did solve the '816 speed problem - it was Sanyo who did the necessary redesign work.
6 Likes
You certainly deserve it!
(Kind of on time for the Olympics, too! Forum posting ought to be an Olympic discipline… 
)
1 Like
Interesting that he didn’t point out that the older Lisa was forced to use a slower 68000 than the Macintosh as an example of what he was talking about.
1 Like
Nice video, enjoyed it a lot. The accelerator Transwarp was mention numerous times, but I was hoping to hear about another accelerator, UltraWarp, which wasn’t mentioned at all. In 2022 I worked with owner of ReActiveMicro to redesign the original UltraWarp so it is faster and more producible. The resulting UltraWarp 2 has 65816 running at 14.7 MHz nominally, but was tested to 20MHz. This is a picture of UltraWarp 2. I don’t think ReActiveMicro ever sell it commercially, probably because there wasn’t much demands.
Bill
4 Likes
I’m surprised that ReActiveMicro can’t sell any UltraWarp cards, because whenever a IIgs with a real Transwarp comes to market here, it tends to go for ridiculous money.
Blockquote
The opcode GALs were the smoking gun for the REP/SEP problem, really. I discovered your thread while doing research—its main contribution was pointing me towards Dave Haynie’s 1990 posts, which then got me to find posts Dave made in 1986 and earlier. It was very helpful on that front!
As I said in a visual footnote, I couldn’t 100% say if Sanyo merely bankrolled a WDC effort to redesign the chip, or if they did the layout work themselves. Mensch has said little about it. The most he says about Sanyo is this in his oral history, and there’s basically no concrete details.
And so then Sanyo, a licensee of mine, they are the best ever, quality, great quality. They were supplying wafers, and I don’t even think I had to pay for some of them because they were a licensee. They wanted to see that it would run on their foundry, so they were testing, packaging, everything based upon being licensed. So I had a complete second source in Sanyo-- I mean, a complete fabless business model with them.
Other details I found were in a 1994 UC Irvine microprocessor report. It wasn’t quoted, but it gave me some insight as to its contemporary fab process in 1994 (e.g. sanyo parts on 1.2 micron and then 800nm). Its history section has some differences from other common reports about the founding of WDC and the creation of the 65C02, which raise a few eyebrows. Either some factual errors or misinterpretations, but I did not rely on those for the creation section. Mensch was doing a PR push around the time of the Sanyo switch, and there are several articles/interviews that give insight to WDC’s business at this time. Most of those other interviews were not referenced in the video but they did help inform a broader picture of that time.
The Lisa was left on the cutting room floor. It’s a very complex system whose architectural shifts actually have some relevance to the IIGS (e.g. starting with the AMD Am2900, the potential 16-bit 6502 derivative from Synertek, Rich Page switching them to 68K, Steve negotiating the deal with Motorola, the Lisa’s bus timing) but it couldn’t be worked in a natural way. The interleaved memory, memory cycle timing, all that stuff had a play as to why it ran at 5MHz despite using an 8MHz part. So yeah, the parallels are there, but that’d make it even longer, with more requirement for coverage, etc…
Burrell Smith getting the Mac’s 68000 to run at 8MHz with its video system—even the fact he was using 68k at all—was seen as a bit of a surprise by accounts from Hertzfeld and others.
The Lisa’s development/architectural shifts don’t get as much play as the Macintosh’s multiple designs and rise to stardom, but it would be something worth its own exploration. I don’t know if I’m the person to do it, but I have enough of a grasp of the facts to at least understand it.
I didn’t mention the UltraWarp because it’s not an Apple IIGS accelerator; it’s for the II/II+/IIe. It’s also a modern accelerator, so it wouldn’t have been helpful for determining the development of historical accelerators. Nothing against the project itself; just that it wasn’t in the scope of the story. I also left out the AppleSqueezer, even though I’m personally interested in that accelerator and have been following it since its inception.
An in-depth exploration of Apple II accelerators in general would be an interesting topic, but it requires a lot of hardware I don’t have, and would be better served as its own story. I also left out the SuperCPU for similar reasons. Theoretically these accelerators could run 16-bit code—at least, they’re claimed to be able to—but I’m not familiar enough with their arch to speak about it.
I have some more thoughts about why certain things did/didn’t happen (like caching, the FPI timings, how a theoretically faster stock IIGS would be made) but they would’ve dragged the pace down further.
Also, thank you all for watching and engaging with the text and thrust of my argument, versus retreating to conventional wisdom. I wasn’t sure how this was going to be received; suffice it to say that the reaction has been much more positive / less controversial than I expected.
3 Likes
Welcome Dan, good to hear some backstory!
I’d personally put much more faith in Sanyo’s ability to make a chip work, and Mensch staying quiet on that front wouldn’t change my mind… of course that’s no kind of historical evidence.
I feel the same way; I just couldn’t find something to 100% confirm that Sanyo employees did the layout and I didn’t feel comfortable factually stating “Sanyo redesigned the core” without seeing the differences. Sanyo absolutely fabbed the newer chips, that’s a fact, and the chip needed to be laid out again to be fabbed on their 1.2 micron and 800nm process. WDC licensed out that redesigned core afterwards, and we have no idea what that agreement looks like. I assume WDC still retained all the IP, but without looking at what are obviously confidential legal documents no one would know this story for sure.
The best way to compare the differences are high-res decapped scans of the Ricoh 5A22 and 5A122 (the SNES original and 1-CHIP CPUs, respectively). The 5A22 has a core that matches up to the one pictured on “Programming the 65816,” while the 5A122 has a core that resembles the more modern designs (post-Sanyo). I’m confident the core used in the 5A122 (and likely the SA-1) is the Sanyo core based on other die photos I’ve seen.
Regardless; California Micro Devices obviously didn’t have that skill, not to mention they were busy ripping the pipes out of the wall based on my reading of the lawsuits that eventually bankrupted them. VLSI was another source of 816’s, but their relationship with ARM in the early 90s meant they probably weren’t going to help either. I don’t think it’s a coincidence that Sanyo wanted to make low power portable or embedded devices and WDC was in need of better fab houses in the 1992 timeframe given those business developments. The partnership seemed natural.
2 Likes
Welcome and thanks for commenting on the video here — and for making it in the first place!
This should be pretty interesting, for sure!
Also, I sometime wonder how easy — or rather, how difficult — it would have been to iterate this architecture in future development cycles…
1 Like
There’s now a discussion about this on Hacker News:
Notably, this is about the related writeup at Userlandia:
1 Like
And of course, gotta love a Vernor Vinge reference thrown in there.