Over the past 18 years, I’ve had the honor of “herding” a highly capable group of “cats” eager to explore and preserve details of the Intel 4004. Most recently my colleagues Klaus Scheffler, a physicist from Switzerland and Lajos Kintli, a mathematician from Hungary got discrete transistor versions of the 4004, 4002, and (sort of) 4001 fully working at 250kHz. I myself re-drew the original 4004 artwork from photomicrographs, with suitable HF acid metal-stripping to reveal transistors. Contemplating doing a 13x die-shrink and submitting it to TinyTapeout. Lots of work to do before that though, since it would have to pass a design-rule checker (DRC). All the best.
Wouldn’t the 4004 have to be converted to CMOS for TinyTapeout?
The TinyTapeout folks now offer an “analog” option which allows for full-custom designs. The problem with my redrawn artwork is that a) it would take a while to fix all the DRC errors, even though we’ve done a significant amount of verification work already, and b) the bootstrap (capacitor) loads would need to be re-designed by a real EE. If I converted it to CMOS it would end up as a “sea of gates” and not nearly as pretty.
I meant that since the original 4004 used a silicon-gate enhancement-load pMOS technology you might not have the right device for a load among the devices supported by the Skywater 130nm process. I fully agree that converting a gate level version of the 4004 to a standard cell implementation would be pointless.
The 4004 was fab’ed using one extra tweak (*) to Intel’s 1970 10um PMOS DRAM process. It offered neither the luxury of depletion nor enhancement mode FETs. Federico Faggin was forced to use sizable “bootstrap loads” (**) to drive strong logic "1"s onto busses, etc. The 8080 designers had access to much better loads, which became the nMOS of lore.
What I’d consider is keeping the bootstrap loads “just for show” but disconnected, and instead using nFETs for critical load transistors (assuming pFETs for regular logic). I haven’t looked to see how hard it would be to find space to squeeze in the necessary wells to surround the nFETs. That said, my recollection from my full custom VLSI design days is that modern CMOS processes put the pFETs in wells not the nFETs. So I might have to flip the polarity of all the the logic compared to the original, using nFETs for regular logic and pFETs for the loads.
(*) Faggin’s tweak was “buried contacts” for a total of 6 mask layers: passivation, metal, polysilicon, diffusion, buried contacts, and vias. I think Faggin had used buried contacts at Fairchild and knew they’d save enough space so the 4004 could be squeezed into the maximum 3x4mm die.
(**) A Faggin bootstrap load was essentially a capacitive voltage doubler: two FETs and a capacitor, relying on the input to wiggle enough to be quasi-AC.
1 Like
Some time ago I decided to recreate the 4004 in an FPGA. I couldn’t keep the voltage levels but one objective was to keep the logic polarity. For me, that was important. Anyone interested can read about it here:
i4004
1 Like
Well done woofy! Very nice project.