I see another EDSAC-in-FPGA has turned up - by Hrvoje Cavrak, MIT-licensed, as a quarantine project. The README also provides a nice overview of the machine.
It’s got 64k of compressed sound effects - no expense spared.
(There’s a link within to a PDP-1 project too!)
It’s in verilog, for MiSTer, which is based on DE-10 Nano.