Wikipedia says, “The reduced instruction set computer returned full-circle to the PDP-8’s emphasis on a simple instruction set …”, but this is wrong, the 8 is not RISC. The key features of RISC architecture are that memory is accessed only through load/store instructions, all computational operations are register to register, there are lots of general-purpose registers, and usually some three-operand instructions. Perhaps the first RISC machine was Cray’s 1964 wonder, the CDC-6600.
A maybe interesting side note to the RISC debate is Ed Fredkin’s claim [1] that a tour to and discussion of the PDP-1 architecture (probably the PDP-1C prototype that went to Triple-I) had influenced John Cocke’s RISC architecture for the IBM 801 and RS/6000 (which evolved into the PowerPC architecture). This would allow to construct a linage from the PDP-1 to the reduced ISA of the PDP-4 to the PDP-8, still somewhat adhering to the original design philosophy. (However, it’s also Ed Fredkin, who was probably a bit biased, being the most ardent evangelist for the PDP-1, and also, well, Ed Fredkin, who built a remarkable career on confident statements.)
[1] YouTube Video (CHM channel), Ed Fredkin at the DEC PDP-1 Lecture, Computer Museum, Boston, Nov. 29, 1990; @22:09 (this is the where the claim is made, but there’s a prehistory to this earlier in the video):
https://www.youtube.com/watch?v=SmYfEnnnBJw&t=1329s
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Very interesting, I’ll have to watch the video. I took a course from Fredkin, Digital Physics, in 1978 as a grad student, and did some original work with him on his Conservative Logic. Sorry, this is a little off-topic on PDP-8 v RISC.
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In this case (as this is now an off-topic thread of its own) may I divert you even further to the CHM oral history of Ed Fredkin? It’s the most amazing oral history, I’ve ever read, and it’s probably even better with personal familiarity:
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A view from a sofa potato. I consider RISC more going back to a Harvard Architecture,
where RAM is mostly internal usage, and the most memory access is Instruction fetching
off of Dynamic Ram modules in fast page mode.
From the advertising of the day, they never said much on the rest of the computer design
for video memory, or multi-user or multi-tasking.
I wouldn’t count the 8 as RISC in the conventional sense. The base argument for RISC was that it was possible to simplify elements of CPU design and propagation delays in such a manner that the overall speed of execution was higher even with more instructions executed than was achievable with complex instructions.
The 8 is from the older “gates are expensive” era. There are machines with elements of both (eg the DG Nova) but they still feel like the ‘RISC’ in the classic sense was a side effect of the budget. The original ARM26 is perhaps the one where both budget and speed converge into something that actually was RISC.
And as memory and CPU speed diverged RISC became a meaningless marketing term because the cost of the instruction fetch rate meant you had to compress the instruction stream and unpack it into operations so CISC and RISC converged mostly into unpack, micro-ops, merge, execute superscalar systems. The one thing that really still survives from RISC today in high performance processors is the fact that flags registers are a really bad idea.
Meanwhile RISC in the academic sense has turned back into “reduced gate count” again with things like RISC V for embedded.
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Fredkin also made that claim in the 1992 Digital at Work official history of DEC, on page 40.
The PDP-1 also helped influence the distant future of computing. After leaving BBN, I started a software and consulting company called Information International, which created PDP-1 applications. Ben Gurley left Digital to join this company, which had its offices in the same old woolen mill as Digital. One day we were visited by John Cocke, the now legendary advanced system architect from IBM. John and Ben went over our PDP-1 in great detail, Ben explaining the intricacies of its design.
Like the TX-0 computer, the PDP-1 had a very limited instruction set. It had been expanded somewhat to make the machine more commercially suitable to a range of applications but, at 28 instructions, it was a very simple set. In the late 1970s, I got a late-night telephone call from John Cocke. (This apparently is his habit, though at the time I thought I was the only one to receive such calls.) John asked me if I remembered the machine Ben had shown him at the Mill in Maynard. I said yes. He said, “I have this idea.” He had worked up a design that was based on the PDP-1. It had a very simple instruction set, like the PDP-1. John had made some modifications; he used a 16-bit word instead of an 18-bit word, for instance. Another change he had in mind was the timing cycle: instead of 5 microseconds it would be 5 nanoseconds. At John Cocke’s insistence, IBM spent more than a decade constructing the machine he outlined for me on the telephone. They called it the RISC System/6000, and over the past several years, its technology has resulted in increasing computing power a few more orders of magnitude.
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