Reverse-engineering an early calculator chip with four-phase logic

An introduction to four-phase logic by Ken Shirriff. This is definitely before my time as my intro to digital logic was with CMOS technology

How four-phase logic works

Four-phase logic is a technique for building logic gates, such as NAND gates. At the time, the standard way of building a logic gate was called “static logic”, because the output remained constant as long as the inputs didn’t change. A disadvantage of static logic was that it required a large “load transistor” that continuously used current, resulting in high power consumption.

A solution to these problems was “dynamic logic”. Instead of providing a steady output from the gate, the gate’s output was controlled by a clock signal. The gate’s value would be computed and then stored by the circuit’s capacitance, instead of requiring a continuous current. Developing with dynamic logic can be tricky, however, because of its dependence on timing. (It also has the disadvantage that the output values rapidly leak away, rather than being stable as with static logic.) Dynamic logic is still used in modern CPUs, in the form of domino logic.

I thought 4 phase clocking (non overlapping) was more that one could use D latches
rather than D flip flops. The 6800 also used dynamic logic in many places.
Only the z80 I think could have the clock stopped.

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I’m afraid I found all clocking schemes confusing if they didn’t boil down to something looking like a single clock and D type flops.

But there was a time when four phase was a jolly find idea, and Ken’s article is a good one!