Technical discussions on the 6502’s Break Flag continue to show misunderstandings and confusion. There’s limits to what a test ROM could prove because someone could still say the break flag is just “hidden” and not directly accessible. So, I am trying to find where on the die to point people to to prove once and for all that the break flag only exists on the stack and not ever in the status register. This link seems to indicate that at some point visual6502 had information on the break flag:
Lower left center, labelled B flag, directly north of decode lines 116 and 115.
Inputs are lines 105 and 106 (PHP/BRK), and D1x1, which is a lovely mess of the B flag, RDY0, phi2, /IRQ, Bxx, and the general interrupt line.
That slew of lines is the data bus, usually pulled high and wired AND’d down I think.
Ok, so it exists after all. But is it really a flip flop, with one bit of state? I’d expect a flip flop to have some kind of never-ending circular path for the bit to circulate.
Can we even be sure D1x1 is an input? If so, why are there two of them coming from down south? That looks more like an output being sent to two places to me.
There is no B flag, there is barely a status register. There are several bits of internal state which track and control what goes on while an interrupt is pending and while it executes.
The visual6502 wiki is terminally broken but most of it is available at the Internet Archive’s Wayback Machine: All pages - VisualChips
The giant schematic by Balazs Berengi is not quite complete and correct, although it can be very helpful, and we have used some of his terminology in visual6502. Balazs’ schematic and documents - VisualChips
Well thanks for the treasure trove that has at least been preserved.
One thing that does jump out to me as strange is that doubly-inverted D1x1. The only reason I can think of to do that is if it lost too much voltage to drive the data bus on its own and needed to be brought back to up to full voltage.
From that first article, the only thing that remotely sounds like a flip flop in there is the word “latch”:
You’ll see that the D1x1 signal latches the pending interrupt, causes the pushed B to be zero, and is then cleared during the vector pull. This same signal is gated by ‘Fetch’ to produce ‘ClearIR’ (which jams zero into the IR)
Other schematics online are clear that a CMOS inverter has both the PMOS and NMOS gates wired together, which isn’t the case here. The two gates for each pair are totally separate.
Is there a name for this special kind of CMOS inverter we see here? It seems simpler than the “standard” CMOS inverter being described online.
CMOS technology was used for the newer 65C02 processor (as the name implies). The original 6502 was fabricated with NMOS technology. As the article you linked to points out, there are two kinds of NMOS transistors: the enhancement mode used for the actual logic and pass gates, and the depletion modes used for the pull-up loads. In a discrete circuit a resistor would be used as the pull-up, but in an integrated circuit resistors take up a huge area in order to have a usable value. So a depletion mode NMOS wired with its gate and drain shorted together is a good approximation of a resistor while taking up a tiny fraction of the space on the chip. Note that because NMOS circuits have an “always on” load, they have a constant current and use up a lot more power than CMOS which only had currents when switching between a 0 and a 1 output or back, which is why CMOS ended up replacing NMOS in the 1980s.
So, if I’m understanding this correctly, the reason that Q2 is an inverter is that when the gate voltage is such that lower transistor makes an open circuit, the supply voltage simply goes through the shorted transistor/resistor and outputs a logic 1. Otherwise when the lower transistor makes a close circuit the supply voltage goes to ground instead, so logic 0.
Q1 is the transistor which allows the storage node to be updated. Q2 is the pulldown in the inverter. If the storage node is low voltage, Q2 will not conduct, so the voltage of the output node will rise because the unnamed pullup transistor conducts. If the storage node is high voltage, Q2 conducts, it has a much lower effective resistance than the pullup, and so the voltage of the output node falls.
The circuit can store a bit of state, and that’s useful, especially as it’s so small. It’s capacitance which stores the charge, and most of the capacitance is actually in the gate of Q2. Some is in the source/drain of Q1, and some is on the wire itself.
(Personally I’ve always found it very helpful to distinguish strongly between two kinds of storage: I use the word latch to mean something which has a transparent action and which is in effect level-sensitive to the clock, and the word flip-flop to mean something which acts more or less instantly and is in effect edge-sensitive to the clock.)
Both the 6502 and the 6800 use a two phase clock, so a master slave flip flop is the
norm. Clock and set/reset could have complex timing like on state control.
There are numerous master/slave bits of storage within, yes, but there are also numerous unpaired latches. There’s lot of interesting detail: transistors are used efficiently.
