Melbourne Train Control System is still running on a hardware "emulated" PDP11

“In this particular train control application it has enabled the life extension of mature train control software, originally designed to run on a now life expired DEC PDP-11 platform to be migrated to a PC based platform. […] Consequently, the major part of the project was the ‘hardware adaptation’ that was required to integrate the new system into the existing fabric.”

Link: https://webinfo.uk/webdocssl/irse-kbase/ref-viewer.aspx?refno=1559669757&document=2.10%20strangaric%20-%20legacy%20train%20control%20system%20stabilisation.pdf

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Here’s the ‘emulator’ card, the Osprey from Strobe Data, an EISA card with FPGA:

Edit: I notice a reply on mastodon…

that emulated PDP-11 system was replaced in 2014-15 by an off-the-shelf “Westrol” system from vendor Invensys

Edit: see also the discussion on HN which includes a link to Strobe Data’s success stories page, and also to this topic-adjacent comment:

My first job out of college in 2007 was building a pdp-11/70 emulator on virtex-5 fpgas to replace the control computers for CANDU nuclear reactors.

We had a punched-tape and microfiche of the xxdp diagnostic test suite to pass…

Several nuances that we replicated were probably never used by the production software. For example the order of execution of a floating point instruction trap followed by a stack pointer trap due to the pipelining of the fpu instructions, even though we weren’t executing anything out-of-order. I also produced the correct partial result for the division algorithm in the event of overflow condition.

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I see that their site does say ISA/EISA, but (at the risk of pedantry) this appears to be a standard ISA card.

Very interesting that this card includes both the PDP-11 in FPGA in RAM, and also an onboard x86 for I/O emulation. It is also interesting to me that it appears to contain both Xilinx and Altera FPGA devices. Perhaps the row of (RAM?) chips in between is to keep them separated to prevent conflict. :wink: It also seems appropriate that the Altera device is the one adjacent to the presumed x86 CPU. (Intel aquired Altera some years ago.)

Since it appears that all of the I/O is emulated, presumably the host PC did the ultimate control. I wonder how it turned out to be more feasible to rewrite all of the I/O control software and design new I/O hardware for a PC but use the original control software. It seems like this is probably a safety-critical system, and I would expect that to require a re-validation of the entire thing.

This entire story is fascinating!

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In the early days Xilinx only made FPGAs and Altera only made CPLDs, so it was normal for a design to mix chips from both vendors. In the 1990s each invaded the other’s territory and currently the terms no longer mean anything.

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