Interesting challenge in a way - not just the challenge of designing a chip and verifying it to the point that you’re pretty sure it will work, but also the challenge of finding the space where a custom chip is going to be better than an FPGA. Now, as the chips are free, the price is a win!
And it seems this process can provide 5V tolerant outputs, and can support mixed signal - although it’s not clear that the libraries are there yet.
Well, these should be faster than an FPGA if you want to go that far.
Honestly, what I would like to see is a Universal I/O chip.
Something that you can plug in to the data bus and a few address pins that opens up the modern world of peripherals: UART, USB, Ethernet/WiFi (w/TLS), up to VGA over HDMI w/sprites. But over a fast parallel bus. An SPI option would be nice, but for a normal legacy CPU, it’s One More Chip in the design (unless you bit bang it, which loses the performance of the parallel bus). The SIO chip has to be clocked 10x higher than the CPU to match the parallel bus. (So, on a 14Mhz 65C816, the SPI has to run at 140MHz).
One Chip Solution. CPU, RAM, UIO chip, separate GPIO chip (this is just a pin count issue). If we can make this chip on a 40 pin DIP, even more exciting.
I still have my eyes on the Raspberry Pi solution, but something less overkill I think would be nice. Unfortunately, it would probably have to be an embedded general purpose CPU with firmware that could be updated, but seems that a full boat Linux distribution is still overkill for a USB and Ethernet driver.