On page 65 of “Programming the Z80”, we have Figure 2.14 Internal Z80 Organization:
The control bus is drawn with an arrow going into the control section (controller sequencer, exactly). But, on the previous page we have:
The control section generates and manages the control bus which appears at the bottom part of the illustration.
On page 4 of the Z80 datasheet, we have:
As each instruction is fetched from memory, it is placed in the Instruction Register and decoded. The control sections performs this function and then generates and supplies the control signals necessary to read or write data from or to the registers, control the ALU, and provide required external control signals.
So, it sounds like the arrow is simply pointing the wrong way? I wonder if anyone has more info on this bus. The diagram seems to be omitting a lot of the interconnections (which is fine, the book warned about that, but they’re good to know about).
I suspect it should be a two-headed arrow, as the various control signals include both inputs and outputs. It’s a very high-level diagram, and I’d say it’s indicative only - it’s a simplification.
Although it won’t answer your question directly, the link below gives the best description I know of about how the Z-80 CPU was really implemented. There are four or five articles packed end to end if you click the link; it’s everything from Ken’s collected work that he labelled “Z-80”.
Yeah, sounds like a lot of signals were omitted just to the register file alone:
To support multiple registers, each register bit is connected to bus lines by two pass transistors. These transistors act as switches that turn on to connect one register to the bus. Each register has a separate bus control signal, connecting the register to the bus when needed. Note that there are two bus lines for each bit - the value and its complement. As explained above, to write a new value to the bit, the new value is forced into the inverters. There are 16 pairs of bus lines running horizontally through the register file, one for each bit.
This kind of thing is fairly typical for manufacturer’s documentation. Another example can be found in the documentation for the RCA CDP1802, another early microprocessor. All the official documentation universally shows the device having an “8 bit ALU”. In fact, each instruction on this CPU took 16 cycles, and 8 of the 16 cycles were dedicated to doing an ALU operation, if any, a single bit at a time; the ALU was 1 bit wide. The result was shifted into the 8 bit wide accumulator, 1 bit per clock cycle, and the programmer was none the wiser.
I think these diagrams exist to help a person build a mental model - they are not a map of the implementation, more an indication of a possible equivalent high-level design. In the days of the 8 bit micro (and before) implementation was very low-level. There weren’t strict layers of abstraction, from the implementers’ perspective. Of course the user - the programmer, the tool-writer, the system designer - doesn’t need to know all that much about the implementation.