I am trying to design a 6809E based system, and would like to implement a unix-style r/w + x memory protection. The datasheet for the 6829 MMU describes how to do read/write protection, but not execution protection. I’d like to extend its system. The way the datasheet describes it is where the upper line of the MMU decoded addr bus is latched to the r/w signal. My best idea so far is to use the LIC signal to determine when an instruction is being fetched, and then use some TTL logic to decode that, and latch it to another one of the MMU lines.
The datasheet describes is a lot better than I can: http://matthieu.benoit.free.fr/cross/data_sheets/mc6829.pdf
Thank you for taking the time to read this.