Has anyone reverse engineered an integrated UART?

[pdxjjb]

In a techie Discord I frequent, there’s an ongoing discussion about a specific technical issue with UART design - the complexity of crossing domains between the UART’s clock and the CPU’s clock. Data races, metastability, and so on.

It would be interesting to know how designers solved this problem in silicon back in the early days. So I wondered if anyone was aware of decapping and reverse engineering a UART, as has been done with a number of 1970s devices.

[EdS]

Have a look at

• 8551 UART dissection //HMOS-II implementation of 6551
  and
• OT: Amiga 8364R7 Paula dissection

(on the 6502 forum)

[pdxjjb]

This answer surpasses my hopes. Thanks so much, Ed. I hope this work survives to future generations (and I hope there are future generations who care).

[oldben]

The 6850 uses the ph2 clock to sync data. if your baud rate clock is correctly generated from
ph1, I don’t see meta-stable problems. The 6502 uart most likely is similar in timing.