Sorry, I have just looked for any material from that project and can’t find any. There might be a copy of the report itself (in Portuguese, unfortunately) is some old Mac floppy but it would be pretty hard to find once I start going to my office again.
This was before Verilog or VHDL were widely available, so the RTL (register transfer level) simulation was done in a Pascal-like language called Lidex created by one of my colleagues.
For the actual chip design I ran into a problem: each user had a disk quota of only 1MB. But the chip synthesis tools would generate up to 6MB of temporary files. There was a temporary area that anybody could use to transfer files between the Windows PCs and the Sun workstations. People had left files there for months and nobody cared. So I did all my work there.
On the day the report was due I went to print the chip layout and found that the temporary area had been cleared. I had the simulation results already printed. So I redesigned the chip from scratch in just 3 hours. It was greatly improved by being far more testable but wasn’t quite working when I ran out of time. So I printed the schematics and layout: if the teacher could tell that the waveforms didn’t quite match those then I would gladly accept him failing me! On the next day all the files were gone again.
It was just the simplistic notion that “this benchmark uses + a lot and I made it 700 times faster, so it should be hundreds of times faster overall”.
Actually doing the math shows that if everything except the + is taking up 33% of the time then the overall benchmark can only become 3 times faster.
They had promised us that if the graduation projects turned out good enough that they would actually be sent to be fabbed though with serious limitations on the area and number of pins. The other groups did simple test circuits with just a few logic gates. An adder takes up enough space that I tried to skip the + at first. Certainly having more primitives would push it over the area limit. In the end it didn’t get made anyway, so I could have just done a far nicer design.