Only the slides are available at the time of writing. Hopefully the video will appear at some point and provide further enlightenment:
So this has nothing to do with Fairchild F8 - Wikipedia ?
This looks great. Tooling-first architecture! From the slides:
- Zero-page, etc addressing isn’t useful if we have efficient stackpointer-relative addressing
- A index-pointer-relative read instruction for both 8 and 16 bits is important
- Prefix bytes can be a good way to allow more operands (e.g. registers)
- Hardware 8 × 8 → 16 multiplication helps
- Division is rare
- Multiply-and-add helps speeds up wider multiplications
- BCD support provides cheap printf without need for hardware division
- Good shift and rotate support helps
And finally
- The core becomes bigger than for RISC, but we save so much
on code memory that it is worth it
Not unless there’s some inspiration taken from it. You would have to ask the author.
Pondering over this … Especially in-light of the AVR/ATmega architecture (cf. Arduino Uno, etc.) which are also 8-bit micros and also designed to be good targets for a C compiler.
New designs are always welcome, but there is a very good port of GCC for the AVR while the f8 is using SDCC - a tried and tested C compiler, but maybe not as well supported as GCC?
However I do note that the system was designed based on SDCC and how SDCC can generate code - an interesting approach rather than try to tailor a compiler to a specific architecture?
What it might be is a good introduction to FPGAs and the Tang Nano 9K in particular…
-Gordon
I think if it’s open source HDL and relatively compact for FPGA usage, it could be rather a good thing.
The video is now embedded in the talk page.