"Examining circuit boards from the Space Shuttle's I/O Processor"

Histories
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Ken Shirriff looks into the remarkable microcoded multi-instruction-set IOP from the Space Shuttle.

The box on the left is the I/O Processor (IOP): the link between the CPU and the rest of the Shuttle. It implemented the input/output capabilities for the computer, primarily 24 high-speed networks that connected the computer to the Shuttle’s systems and sensors. But the IOP wasn’t just a peripheral; it was a separate programmable computer, more complicated than the main CPU. The IOP had an unusual architecture: it was one of the first multi-threaded computers, implementing 25 virtual processors (with two completely different instruction sets) that ran on one physical processor.

The IOP being microcoded is one thing, but having two very different instruction sets, and time-slicing between virtual processors, is rather interesting and unusual. Here’s a picture, showing a band of 33 time slices, advancing every half microsecond, where the MSC machine gets about 1 in four slots and each BCE machine gets one slot each, with the 33rd slot described as spare:

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The I/O Processor’s slot timer or “wheel”. Adapted from Space Shuttle Systems Handbook, 8.3.

Ken writes:

How do the MSC and BCE processors all run on one physical processor, when they have completely different instruction sets? The trick is microcode: each MSC and BCE instruction was implemented in microcode, through a sequence of 72-bit micro-instructions. A simple instruction might take five micro-instructions, while a complex instruction might require 60 micro-instructions. Each micro-instruction directed the action of the IOP’s physical processor for one step of the MSC or BCE instruction. After each micro-instruction, the physical processor switched to the micro-instruction for the next virtual processor. The architecture of the physical processor was completely different from the MSC or the BCE: three 16-bit data paths and two ALUs (Arithmetic/Logic Units) that can operate in parallel. The physical processor had a separate register set, including a micro-instruction address register, for each virtual processor, to keep track of the state of each virtual processor.

The physical design is also interesting: pairs of PCBs back to back on a heat sink with a heat exchanger to air cooling at each end (as far as I can tell.)

2 Likes
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It is pretty much beyond my comprehension that the Space Shuttle — first flown in 1981 — used magnetic core memory.

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Given the density and cost of semiconductor memory at the time design of the shuttle computer started (years before 1981), magnetic core probably seemed a good idea.

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I thought it was the NONVOLATILE aspect of core was needed, in case of a major computer failure
as well as CORE is radiation resistant.Ben.

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And yet - there’s usually quite a long design pipeline for spacecraft, so the design date will be much earlier. And the process is very risk averse, so keeping up with developments isn’t a priority.