Building a TMS 9900 Homebrew

This post (to be thread?) is an outline of how I came to build a TMS 9900 homebrew computer on my desk at work (I work at university, teaching Computer Science), and what casual digital retrocomputing homebrew can look like in the current era. I previously wrote up some information about the TMS 9900 platform itself on this forum, for those who are interested.

Some time in late 2019 or early 2020, I decided to build a TMS 9900 homebrew computer, but I didn’t move on it immediately, and Spring of 2020 my work was forced online and I took up residence in my basement, further cluttering my work space, putting the idea on pause. Eventually, however, I ordered parts on eBay, and started work. I think the impetus to stop thinking about it and actually order was a discussion with @EdS on this very forum, although I couldn’t find the particular message.

I have been doing my work using mostly period-appropriate equipment, although some equipment that would have been out of the price range of a homebrewer at the time. That includes:

  • Solderless breadboards
  • A bench DMM
  • An HP 1630G logic analyzer (this would have sold new for tens of thousands of dollars in the early 1980s, but a significant portion of my purchase price was shipping and handling!)
  • A Tektronix 60 MHz analog 2-channel 'scope
  • A Tektronix 100 MHz analog 4-channel 'scope
  • A Tektronix 100 MHz analog / 100 MSPS digital storage 'scope (I believe this was released in the late 1980s, so probably anachronistic, and also certainly out of the hobbyist’s price range at the time!)

By early July of 2020, I had built up the basic requirements for a TMS 9900 system on a breadboard, including an oscillator, four-phase clock generator, and reset logic. I took some time to learn my equipment, some of which I had had on the shelf for a while, but not really had a chance to use in anger. One of those pieces of equipment was the HP 1630G Logic Analyzer, a 65-channel 25 MHz standalone logic analyzer.

Here is the analyzer viewing the 12 MHz input and 3 MHz four-phase output of the TIM 9904 clock generator used to clock the TMS 9900 CPU.

By late summer of 2020, I had a basic computer assembled on the breadboard, and could boot and run simple code, observing its operation on the logic analyzer. Due to the TMS 9900 architecture, it is essentially impossible to trial the processor without, at minimum, a half dozen to a dozen chips; because the processor has no onboard register file, you must have RAM to run any interesting instructions, and the processor must load several locations from ROM in order to set up those registers. This entails clock generation, the CPU, a 16 bit wide RAM (or 8-bit with decoding and a latch for the other half of the bus), a 16-bit wide ROM (ditto), and decoding to address RAM/ROM. I happily continued this buildout while watching VCF West online in 2020:

(This is the space in my unfinished basement that I shared with my online teaching setup for March of 2020 through the 2020-2021 school year. As you can see, it was not ideal!)

By the end of VCF West, I had a “complete” system with clock, processor, RAM, and ROM, although the only way I could see it in operation was by watching the logic analyzer, and it wasn’t yet booting properly.

Note that, by this point, my “oh I’ll just stick this on a breadboard real quick” methodology is already starting to become questionable. It’s difficult to tell in this photo, but there are three power supplies coming in (the red and black banana leads on the left provide +5 V, the red wire flying in across the logic analyzer pods top center is +12 V, and the dark green wire coming across the same pods is -5 V), and the data/address busses have already spilled over onto a detached breadboard for the RAM and ROM (visible at the bottom, surrounded by mostly white and green wires). I did manage to keep my ROM chips mostly exposed, so that they can be easily removed for reprogramming.

By the next week, the processor booted and communicated with an external TMS 9902 UART, as memorialized by this photo of a Tektronix 4010 graphics terminal that I was using as its console:

The fragility of the design, however, had grown even more significantly, with a second floating breadboard holding the interrupt controller and UART and providing the CRU (serial peripheral bus) decoding logic. Let’s call this system the TIC Mk 0.

By this point, I was developing a boot monitor for the machine (there is a TI monitor called TIBUG available as scanned sources and an OCR’d version from at least one place on the 'net, but I am not (yet?) trying to use it), but development was getting frustrating. The computer was very fragile, and frequently I would spend time chasing after loose connections and dislodged probe wires, rather than doing software development. This was a consequence of having never intended to build up a full working computer on these breadboards, but rather letting some idle puttering grow and grow until it booted.

The logic analyzer and digital storage 'scope were both indispensable in getting to this point. I don’t know that I could have done it, without them – or at least that I would have had the patience to do so. I fought a problem with clocking that was eventually identified with an analog oscilloscope, but some memory/bus issues and problems with a faulty TMS 9902 required the logic analyzer and the DSO, respectively. In particular, the faulty TMS 9902 lost me literally days of development; I am a seasoned enough software developer to know that it’s never the existing code, which I extrapolated to the existing hardware. It turns out that when that hardware is several decades old and purchased as pulls from a Chinese scrapper in Shenzhen, it might be the hardware.

I stalled out on this project some time that fall, and stopped working on it; the fragility of the system was just too frustrating, and other retrocomputing projects took up my hobby time. I worked with my PDP-11/34A hardware, re-capped and cleaned up an Osborne 1, toyed with Beagle Bros’ Program Writer and Microsoft CP/M on an Apple ][, and other diversions instead. Why fight flying leads and dislodged I/O lines when I could play with something that worked? However, I a) wanted my workbench space back, and b) wanted to continue proving out some access and bus logic to have a 9900 PC board built that I could use to put together a complete system.

So in the fall of 2021 (about one year later) I gathered up all of the parts that I would need to build a more robust (yet still solderless) implementation, and started reproducing a slightly more complex version of the same system on my desk at work. I am privileged to work in an environment where I can tinker in my down time (though I’m not being paid for that time, but it makes sense to be there anyway, so is that really privileged?), so I swept the usual detritus off my academic workspace and replaced it with vintage components and solderless breadboards. By early 2022, I had a complete replacement plus additional bus buffers and related logic put together in a much more robust configuration and ready to start debugging; we’ll call it the TIC Mk 1.

It is immediately obvious that the Mk 1 is a more pleasant environment to work in than the Mk 0 had become! The breadboards are all affixed to the same surface, there is more breadboard space to work in, and the wiring is all measured and cut very neatly to remain mostly out of the way when working and probing. The CPU itself is rather buried, but most other chips can be easily removed and replaced. On this board, green wires are address lines (buffered or unbuffered, but not decoded), blue wires are data lines (buffered or unbuffered), yellow wires are clock, white wires are miscellaneous control signals, and red and black have their usual meanings.

Here is the same board, but with some labels showing where the various parts of the system are laid out:

Note that the entire board runs on a single +5 V supply, and the necessary +12 and -5 V supplies are generated by a switching DC-DC boost converter and a charge pump supply inverter. This is fine for breadboard use and plenty of current is available for both of these purposes, but in the final system (with disk drives and such on the 12 V in particular!) I will use an external multi-voltage power supply to provide these things. It is fortunate that the TMS 9900, while being an NMOS processor that requires a substrate bias, is forgiving about the timing of its positive and negative voltage supply provisions, so I do not have to build a staged power supply. Additionally, by using static RAM, I have eliminated the necessity for a negative supply for (period) DRAM chips and the associated timings for that purpose.

This, of course, did not boot. I wound up having to haul my logic analyzer in to work and hook up the oscilloscope that normally resides on top of a cabinet, and soon the patient looked like this:

That is obviously decidedly less pleasant to work on, but it quickly gave me some useful (though puzzling) information: The processor was doing something that was not entirely unreasonable, it just wasn’t a normal boot sequence. This gave me some confidence that at least the supplies and clocks were doing something (it turns out the latter was a problem), but clearly something was not correct.

The TMS 9900 is a bit of a strange beast in that it loads address 0000h and 0002h when power is applied, and it gets its workspace pointer (the location in RAM where it will store its general purpose register file) and the starting PC value from those locations, but it also uses addresses 0000h through 0100h for interrupt and extended operation (think software interrupt) vectors, which, on a system with a general purpose operating system, almost certainly need to be in RAM. Contrast this to the 6502, which uses a zero page at 0000h through 0100h that usually must be in RAM, but loads its boot vector from FFFEh and FFFFh. This allows RAM to be located at address zero, and ROM the top of memory space. For the 9900, you almost need both RAM and ROM at address zero! The TIC Mk 0 (my first floating breadboard design) used a latch to redirect the ROM bank to the bottom of memory until the processor loads its first instruction, at which point it was shoved to the top of memory and RAM was addressed at address zero. However, the 9900 also has a LOAD line which, when brought low, causes the processor to load a workspace pointer and PC from addresses FFFCh and FFFEh; much more convenient! The Mk 1 is configured to latch LOAD low until the processor fetches its first instruction, and RAM is always low in memory while ROM is always high in memory.

All of this is to say that what I should have seen was a fetches for 0000h and 0002h, then fetches for FFFCh and FFFEh, then the instruction acquisition line (IAQ) going high and the processor loading the first instruction. Instead, I saw this:

The LOAD line is not visible here, but it was zero from reset until IAQ went high, just as expected. However, the processor was asserting address zero on every single clock cycle! Memory enable (labeled -MEM here) was correct, but the address and data being fetched were always 0000h. Since RAM is at 0000h, the data could reasonably be nearly anything, but we should at least see a fetch for 0000h followed by 0002h, and we do not. There is certainly no attempt to access FFFCh and FFFFh, and it appears to begin executing immediately at the loaded PC of 0000h! Something is definitely fishy.

Remember, way back in the discussion of the Mk 1, when I said that I had to use an oscilloscope to debug a clocking problem? At some point the back of my brain started to tickle on that issue, and I remembered having seen a similar trace in the past. That caused me to put the four phases of the +12 V TMS 9900 clock on the 'scope, where I found this:

The lower trace in this image is ϕ1, and the upper trace is supposed to be ϕ3, of a four-phase clock where each phase should be 90 degrees from the previous. Note, however, that ϕ3 is immediately leading ϕ1 (270 degrees), while it should be at 180 degrees! I had crossed ϕ3 and ϕ4, which was (apparently) breaking address setup!

Take a look at the pinout of the 64-pin TMS 9900 to see how this might happen:

A line diagram of a 64 pin DIP package labeled TMS 9900 Pin Assignments at the top.  Pins 8 and 9 are Phi 1 and Phi 2, while pins 25 and 28 are Phi 4 and Phi 3.

Note that the linear order of the four phases down the side of the chip is … ϕ1, ϕ2, ϕ4, ϕ3! I wired them in 1-2-3-4 order, when they should have been 1-2-4-3. After fixing that, a few minor wiring and logic bugs were uncovered by careful inspection, and unreliable attempts to boot were identified.

The most recent bug to fall (just before leaving the office on Friday of this week) was a high-impedance connection between two breadboard grounds, causing one of the logic chips’ low states to rise over 1 V from the perspective of other chips, which was into the linear region of the IC and causing havoc with signaling. After fixing that, the expected fetches to 0000h, 0002h, FFFCh and then FFFEh showed up on the logic analyzer.

I have high hopes that the Mk 1 will achieve UART communication early this coming week, and that additional software and hardware development can continue in earnest. The purpose of the Mk 1 on a breadboard is to prove out memory and bus management designs in a flexible fashion, so that I can lay out a PCB that will serve as a suitable development platform for an extended period of time (both because it will be more reliable than the solderless breadboard design, and because it will have had most of its kinks worked out before it was etched!). The ultimate goal of the system is to provide: a video console (80 characters) with keyboard, serial I/O, mass storage (both floppy and hard disk, possibly IDE or ATAPI), FM synthesized sound, and the other trappings of a mid-1980s computer. (The TMS 9900 dates from the mid-1970s, but my desire for things like 80 column video and reasonable FM sound pushes my parts collection to the mid 1980s.) Hardware like the video console, disk controllers, and sound device will ideally be provided through cards in a slot architecture. (If I wanted to keep it real with the TMS 9900, I might provide only a single slot, and make them daisy chain!)

I hope to provide additional updates on this journey; I wish I had started this thread a year and a half ago when the project began, and I anticipate additional multi-month stalls as real life interferes with hobby life, but seeing others’ journeys in homebrewing has inspired me to take on this project, so I want to give back some of the story and information. I’ll try to update my TMS 9900 thread with more CPU and architectural information as I go along, as well.


For those who are interested, the BOM cost of this system is somewhere around $60 (not counting the solderless breadboards) as it stands now; the CPU and CRU peripheral devices were bought as pulls from a Chinese supplier for about $25, and the 28C64B ROM chips are the next most expensive components at about $4 apiece. The other ICs were either bought surplus or are simply much less expensive. The remainder of the cost (about half of the total) is divided between those other ICs and the wire itself; there’s somewhere around 60 feet (somewhat under 30 meters) of wire on that board, by my estimate. Almost half of it is green!

As these things go, I have much more than $60 in it, but in consequence I have enough parts to build several identical systems less the CPU itself (for which I have only two units, one for the Mk 0 and one for the Mk 1, and no spares).

The solderless breadboards were about 3 for $8 on eBay, and the base is hardboard from a home improvement store.

If I had it to do again, I would solder together at least the ground buses on the breadboards. The signals on the board honestly look pretty good, but keeping ground impedance low has been a challenge. Between simple resistive connections in the jumpers and the long path for return current, raised and bouncing grounds are causing me some headaches.


Great write-up and excellent adventure. So glad you didn’t get stuck on having made too much progress to write it up.


Very nice! Looking forward to updates…


Yes, great write-up. Thanks for this story, I really enjoyed reading it.

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Congratulations on interesting homebrew computer project.

Now that you have a core CPU group working, one thing I recommend is building a PCB for it and plugging it into your breadboards for the rest of the expansion and testing phase. A PCB, especially using 4 layers, will dramatically improve ground and power rail performance. Overall reliability and repeatability as well. You can build diagnostic and debug features into your PCB and even plated through-hole expansion areas. PCBs from JLCPCB are inexpensive enough to be disposable so if there are errors just respin and try again.

With modern EDA tools like KiCAD you can iterate PCB versions and grow the system outward without the flakiness and mess of breadboards. In addition, using KiCAD means the design is now repeatable since you can post the files to a Github repository and let other people share in your project.

Probably you already know how to do all of this but if you’d like I’m willing to help. It sounds like an interesting project. Good luck


Thank you for your response and your feedback!

Yes, the next phase is absolutely to move to a PCB. I will probably use a two-layer PCB (because it would have been more likely for an early 1980s computer approachable in homebrew), but I am not entirely opposed to moving to four layers if it dramatically improves layout or if two layer has undesirable noise problems.

[Everything after this is speculative!]

The plan is (and has always been) to lay out a PCB with a slot architecture for the Mk 2. I have not yet chosen a slot or a final bus design, but I anticipate needing 56–72 pins (the processor uses about 59, and I will need multiple ground returns as well as some extra pins for bus arbitration and interrupt lines). The goal for the slot architecture is to allow a slotted card to use DMA for memory mapped I/O, the CRU for low speed I/O, and interrupts. This will require about 31 address and data lines, half a dozen memory control lines, half a dozen CRU lines, and a handful of open collector interrupt signaling lines. Slots will probably provide only +5 V and ground, and the motherboard may have a few 12 V PSU headers for cards that need other voltages.

Before laying out that “motherboard”, I would like to experiment a bit with some memory management logic; right now, I have four “banks” of RAM of 16 kB each, three of which are RAM (only one populated) and one of which is ROM. This is very wasteful, and does not leave a convenient space for memory-mapped I/O. I would like to reduce the mapping of the upper 16 kB into smaller chunks, with options such as shadow RAM behind the ROM, and a dedicated space for MM I/O. (Possibly using 4 kB chunks of the 16 kB space.) This is easily done in combinational logic, except for deciding how to negotiate MM I/O space (or perhaps it will not be negotiated, but simply turned on and off?).

The goals for this breadboarded system (as opposed to the eventual, completed computer) are:

  1. Proving out the bus architecture enough to suspect that I’ll be able to at least make progress once I spin a board
  2. Showing students and other homebrewers an example of what you can do on solderless breadboards with minimal parts
  3. Demonstrating the architecture of a computer in a real way that can be touched – “the address bus is these green wires, and these blue wires over here are the data bus”

Once I have a basic CPU board with at least one slot, I will build a slot adapter to attach to a solderless breadboard, as you mention, and I will begin designing peripherals on breadboards.

I anticipate the time frame to having an actual slotted peripheral will be … long. :slight_smile: I am currently considering an ATAPI adapter as my first I/O device, as it will exercise MM I/O and interrupts, and provide the possibility of DMA, while giving me access to an extremely convenient data transfer mechanism and bulk storage – CD-ROMs and Iomega Zip disks. My original plan was to build a floppy disk system first (I have some WD double density floppy disk controllers), and that is also a possibility, but the attraction of working disk control electronics out of the box is large.

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I’ve built numerous homebrew systems. Some are all-in-one planars and others are bus-based using cards for each function. Both have advantages and disadvantages. At least while starting, I would go with the all-in-one until you’re confident the core architecture is working reliably. Two layer PCBs will work fine assuming the clock speed is fairly low like 10-12 MHz max. Beyond that I would recommend 4-layer PCBs.

I think something important to remember when designing bus-based systems with a large parallel backplane is to fully buffer the CPU core driving the backplane and the cards themselves. It is very easy for little mistakes to creep in and buffers & transceivers will save your system from self-destruction. It is much cheaper and easier to replace a 74LS244 than one or two of your capital chips.

Also the buffers and transceivers are built to withstand amazing levels of abuse that the capital chips just cannot tolerate. By capital chips, I mean RAM, ROM, UARTs, CPUs, DMAs, or any other of the big chips that make the system go. Some people may disagree with the need for fully buffering but all you need is one little slip and you can fry a lot of expensive parts if you go unbuffered. I think buffering makes the system overall more reliable and resilient by isolating the processing elements from the electrical no-mans-land of the large parallel backplane.

When designing a backplane bus it always seems like eventually you’ll need more pins. For certain replicate the primary signals on the CPU but there are usually other signals where the need arises like prioritized interrupts, DMA, sometimes utility signals like chip selects and serial comms such as I2C, etc. So if you CPU is using ~60 pins then I would allow for a decent amount of spare. Usually ground and power are 2 or 3 pins each.

Do you want to generate +5VDC locally on the card or supply from the main power supply? Generating locally using a voltage regulator (or equivalent) will prevent rail sag on a big system although it adds components like VRs + capacitors, diodes, etc. So it is a trade-off.

I would save the bus-based system until after you have a robust all-in-one planar built up. I have examples of both systems if you want to see them as examples. Based on Z80/Z180 but the principles are the same.

I hope you set up a Github repository for your TMS9900 design so others can see your work. At least post schematics and layout information so your efforts don’t get lost in the churn. Using KiCAD really helps document and preserve designs because it captures it in a portable, non-proprietary, open-source format that can be reused and recycled. So many great hobbyist designs have gotten lost over the years it is a real shame. Similar if you decide to use GALs or CPLDs, please publish the JEDEC source in the schematics so they don’t become mysterious “black boxes” in the future. Personally I try to avoid use of PLDs unless absolutely necessary although they do have their place.

Sorry, one more thing I forgot to mention. Bread boards are nice in that they can be built and modified easily but they are a pain to maintain and can be delicate. With some fore-thought PCBs can be easily modified too by lifting pins, using flying leads, trace cuts & jumpers, dead-bugs, etc. Exporting signals to pin headers and adding PTH zones for prototyping will help the debug process. Adding diagnostic LEDs are a big help too plus user input buttons, beepers, etc. Also for the first iteration or two I would avoid the use of fill-zones (aka copper pours) because they make separating a pin from ground rather difficult.

The cost of PCBs have gotten very affordable of late. I recently ordered a set of 5 PCBs (8"x11") from JLCPCB for less than $30 plus $30 for shipping. So $60 for 5 PCBs to proof out a design is pretty affordable. For my other system which uses 100x100mm PCBs, they only cost $6 for 2 sets of 5 PCBs (order 2 board sets at a time to save shipping) plus $14 shipping is about $20 for 10 PCBs delivered. That’s pretty reasonable. Of course the smaller boards are single function so there are many of them whereas there are fewer of the big planars. It just depend on the project. I think your current design is headed towards the big planar solution at least initially.

The TMS 9900 is capable of operation at no more than 4 MHz, although a 4 MHz system has 16 MHz clock pulses because it uses a four-phase clock. The parts I am using are 3 MHz (with 12 MHz clock pulses). The signals look just fine even on the breadboard. With buffer drivers and a reasonable board layout, I anticipate no trouble with a two-layer board.

On the system I am currently building, the TMS 9900, its interrupt controller, and the console UART will be connected without buffers. The memory and all bus devices are behind '244 and '245 buffers from the CPU. On the breadboard there are no buffers between the memory and the “slot bus”, but I plan to include them on the memory data lines in the PCB design, because the TTL (even LS) fanout of the SRAM chips is not large.

The calculations in my previous post enumerate interrupt and serial (CRU) lines, as well as the necessary CPU signals; my calculation of total necessary signal lines is somewhere in the neighborhood of 60, and I am sure I will identify a few more before I am done (in particular for DMA). I am tempted to also include a slot ID on each slot, as well as a slot selection field, for enumeration and auto-negotiation, but I think that might not be a Mk 2 feature. :slight_smile:

I plan to provide +5 V from the slot, and I anticipate having only a small number of slots. I may provide accessory power connectors, as I said, for cards that need more – but I don’t really anticipate having cards that need more power, as perhaps cards that need more flexible voltage generation. Power supply generation, however, is something that I do not mind solving with anachronistic solutions. I will use a period-similar switching power supply (I have some aftermarket Apple II power supply units) for system power, but I don’t mind some buck/boost converters on I/O boards if they need them. Linear regulation is just too power hungry and hot to justify building something S100-style unless you’re really keen on period correctness.

I will absolutely publish the design once something stabilizes. I am using KiCad for layout, and thus far I am using an open source cross-assembler with TI syntax for development. At this point I do not plan to use any GALs or PLDs, although as very small ROMs are difficult to obtain, I may compromise and use PLDs where a period system might have used a 64–512 byte PROM since the PLDs are readily available.

When I order my first PCBs, I intend to include the CPU, a full complement of RAM + ROM (including bank switching), an interrupt controller and limited GPIO, and a console UART on-board at minimum. I will also lay out a number of 16- and 20-pin spare footprints with convenient power and ground for bodging in additional logic, and possibly a prototyping space. I regret that wire wrap sockets are so expensive, or I’d plan for wire wrap prototyping. I have no target board size, but I’m guessing somewhere around 8x6" minimum to your 8.5x11" at maximum, with 3–4 slots. My goal is to have 100% of the hardware that I need for monitor and operating environment development on a single board, with an addition of one mass storage board in a slot to get me to self-hosting. While I doubt I will self-host primary development (if nothing else, I have no desire to write an editor that is more than a line editor, particularly in assembly), it is a goal.


Reminds me of several instances in my automotive maintenance and repair career where “he who shall remain nameless” somehow messed up a four-cylinder ignition firing order … :upside_down_face: the majority of them started and ran, but something was dreadfully wrong.

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Well it sounds like you’re off to a good start. Congratulations on your project and let me know if I can help. Thanks and good luck!

PS, I was searching through my collection of ICs while looking for something else and noticed I have an ancient TMS9900 CPU in DIP-64. I think it has been just waiting for a project like this to come along so it can find a new job in a home brew computer


Very interesting, indeed. I’m looking for a (simpler) project. But the more real hardware, the better. I especially like the green terminal. But someone needs enough time, money and space. And skills and the other equipment. OK time, you might take, but for the rest…

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Space and skills are moderate for this build. One nice thing about this board as it is constructed is that I can easily just pick it up and move it around, and then put it back and it still works. You do have to be able to store it somewhere where it will not have its wiring disturbed. I am a computer scientist by trade, not a computer engineer – the electronics on this board are very approachable by anyone with a Radio Shack Engineer’s Mini-Notebook from the 80s level of electronics skill. (Not intended to put down those notebooks or Forrest Mims’s excellent work!)

The cost is not negligible. As I said above, the BOM is probably about $50, but that was achieved by buying some parts in quantities of a number of units, and it doesn’t factor in shipping (which can be avoided for some things, but not others). Add the breadboards, and you’re probably talking an outlay of about $100–150 US just for the electronics, wiring, and boards if you have to buy everything special for this project. That’s not nothing, but it’s also fairly affordable if you’re building it as a long term project. If you don’t plan to spend a lot of time using it once you’ve built it, it’s a large investment.

Equipment … is the real killer here. You can technically get away with a pair of needlenose pliers, plier-style wirestrippers, and a ruler or pair of dividers and very little else in terms of hand tools, and a DC 5 V power supply and commodity PC with a $15 USB serial adapter in terms of electronic tools. However, I think it would be very, very difficult to achieve success with such a setup. A (cheap, low-bandwidth) oscilloscope is probably a necessity, and a modern DSO would help a lot. I’m using a vintage commercial logic analyzer, but you could get by with an Arduino or STM32 Discovery and some relatively simple software (some or most of which already exists as open source offerings) without too much trouble – which is both much cheaper and much smaller than a 1980s logic analyzer, and much, much cheaper than a more modern logic analyzer, and probably easier to use in some ways, but definitely more difficult in others. All in all, I think it’s fair to say that the minimum outlay of $50 for just enough equipment to complete the job if nothing goes wrong would end in frustration and tears, and that in actuality you’re going to need to spend more on test equipment than on the computer itself – and set aside a small cupboard to store it.

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Following your progress on this project. Very interesting to use the TMS9900 which I think has been an underappreciated processor.

Assuming you release a PCB for a project some day, what special and/or unique parts should I be obtaining to do this build. Obviously a TMS9900 processor but any particular kind or package? I have a TMS 9900 in DIP-64 package so a least a DIP-64 socket. Any other special parts? You mention a TMS9902 UART and a CRU. Any other specialty parts? I am not asking about common SRAMs, Flash ROMs, 7400 series chips, etc. since I either have those already or can obtain them easily.

Maybe start a Github repo and post a “planning BOM”? Thanks

PS, maybe consider adding a TMS9918 for video output? Console video is very handy and era-consistent with the TMS 9900. Also I have some just waiting for use in a cool project

So far the only parts that are not standard JEDEC RAM/ROM or 74ls logic are:

  • TIM 9904 (74LS362) Clock generator. This is a SN74-listed part, but I doubt anything but the TMS 9900 line ever used it, so in practice it’s available only from TI.
  • TMS 9901 I/O and Interrupt Controller. This is a CRU-interfaced parallel I/O chip (think 6522 VIA or 8255 PPI) with a counter-timer (like the 6522) and priority encoder.
  • TMS 9902 UART. This is a CRU-interfaced TTL-level UART. Paired with a Max232 or similar, it provides an EIA/RS-232 serial port.

These three chips are available from eBay sellers in a “kit” with the TMS 9900.

In addition, you need +5, -5, and +12 V rails, at a total of about 250 mA or more if sourced from the +5 V with converters (less if you have a dedicated 12 V supply). I drive mine using a Lambda bench supply at +5 V, with a small four-pin switching DC-DC converter for the +12 V and a voltage inverter charge pump for the -5 V (which requires only microamps to maybe single digit milliamps).

I went the kit route for Mk 0, and then came back and bought individual components for Mk 1.

I’ll have to let you know what I choose for the other parts of the system; I have some Motorola 6845s laying around that I might try to use for video, and some Western Digital I think 17xx that I might try to use for drive controllers, but all of that is still up in the air. The TMS 9927 is a more likely choice for me than the 9918 (because I want 80 column text) if I go TI; other contenders are the NEC 7220 or the Yamaha V9938 (which is mostly backward compatible with the TMS 9918, but has a fast enough pixel clock for 80 columns).

Like this chip kit on eBay? TI TMS99xx Kits TMS9900 + 9901 + 9902 + 9904 + 6264 + 62256 + 27C64 + W27C512 | eBay

I already have the CPU but since I have no idea where I got it there is a non-zero chance it is a dud so having a spare is probably a good idea. Plus, I like the idea of all the parts bundled together increasing the chances these will actually work together. Save these for the hope chest of future projects

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Here’s another 99xx-based computer: . Note that this uses the 9995 rather than the 9900, which makes it easier to interface (single supply voltage, among other things)

Yup, like that! There are usually several kits floating around at any given time, with different support chips. Sometimes they will have a 9918, or two 9901s versus one, or a smattering of jellybean logic.

Not sure how an MC6845 would work with TMS 9900 but most designs assume shared memory architecture so that adds a complication. If you want 80 columns TMS 9918 is not good but has been paired with TMS 9900 in the past.

The successor chips (V9938/V9958) would make sense especially the V9958 which is similar to TMS 9918 interface-wise but expressly supports 80 column mode.

I wouldn’t recommend uPD7220 because that subsystem will be as large as the rest of your design unless you want to double the size of your project. I am doing a Z180 GDC project which is basically a uPD7220 with an Z180 SBC attached.

You might consider an SY6545 or derivative because it is MC6845 compatible but is accessed by regular IO port (not shared memory interface). There are a bunch of these. I made a ECB VDU board based on SY6545 which is still on RBC wiki & forum.

BTW, the next two boards for the Z80 MBC project (nhyodyne) will be a pair of V9938/V9958 variant boards. Need to finish the Z80 PRINT and Z80 PSG boards first though plus there is work underway on Z180GDC (rhyophyre) so I don’t want to overload with too many boards at once.

Do you have a schematic for the TIMS9900 homebrew computer youo have now? If so, will you post it?