Building a hybrid Z80-6502 with ChatGPT

So, I got myself wondering sometimes about some “what if” scenarios… One of such is trying to conceptually build a “ultimate 8-bit CPU” and since I don’t have the knowledge to do it myself, I often found myself talking to an AI about it. This conversation evolved to a more “feasible” exercise: trying to merge the Z80 and the 6502 while maintaining the strengths of both. This was the result:

ME: “If we were to merge this two processors[the Zilog Z80 and the MOS 6502], how could we capture the strengths of both and combine into a singular CPU?”

CHATGPT: "Merging the Zilog Z80 and MOS 6502 into a singular CPU would involve capturing the strengths of both processors while potentially mitigating their individual weaknesses. Here’s a conceptual approach to combining their best features into a new hybrid CPU:

Key Strengths to Capture:

Zilog Z80:

  • Rich Instruction Set: Provides powerful instructions for data manipulation, arithmetic, and control.
  • Versatile Registers: Multiple general-purpose and special-purpose registers for flexible programming.
  • Interrupt Handling: Sophisticated interrupt system with multiple modes.

MOS 6502:

  • Simplicity and Efficiency: Simple and efficient design, making it easier to program and implement.
  • Fast Memory Access: Efficient use of memory with fast access times.
  • Low Cost and Power Consumption: Cost-effective and power-efficient design.

Conceptual Hybrid CPU Design:

Core Features:

Instruction Set:

  • Combine the rich and orthogonal instruction set of the Z80 with the simplicity of the 6502.
  • Include the Z80’s advanced instructions (e.g., block transfer, bit manipulation) while maintaining the straightforwardness of the 6502’s instruction set.

Registers:

  • Utilize a versatile register set inspired by the Z80, including general-purpose registers (A, B, C, D, E, H, L) and index registers (IX, IY).
  • Incorporate the 6502’s efficient use of a small number of registers (A, X, Y) for specific tasks.

Addressing Modes:

  • Provide a wide range of addressing modes similar to the Z80, but ensure they are easy to use like those in the 6502.
  • Include direct, indirect, indexed, and relative addressing to offer flexibility.

Interrupt Handling:

  • Implement the Z80’s sophisticated interrupt system with support for multiple interrupt modes (NMI, INT).
  • Maintain the simplicity of the 6502’s IRQ and NMI for ease of use in less complex applications.

Clock Speed and Efficiency:

  • Design the CPU to support high clock speeds, similar to advanced versions of the Z80.
  • Optimize for low power consumption and cost-efficiency, inspired by the 6502’s design philosophy.

Memory Management:

  • Use a 16-bit address bus to address 64 KB of memory, with potential for memory banking to support larger memory spaces.
  • Implement fast and efficient memory access patterns, drawing from the 6502’s approach.

Backward Compatibility:

  • Ensure backward compatibility with both Z80 and 6502 assembly code to leverage existing software libraries and applications.

Architectural Design:

Data Path:

  • Design a unified data path that can handle the 8-bit operations characteristic of both processors.
  • Include an ALU capable of executing both simple and complex operations efficiently.

Control Unit:

  • Implement a control unit capable of decoding and executing the combined instruction set.
  • Use microprogramming to handle the more complex instructions from the Z80 while maintaining the simplicity of the 6502’s control logic.

Pipeline and Performance:

  • Introduce a simple pipeline to improve instruction throughput without significantly increasing complexity.
  • Optimize the fetch-decode-execute cycle to minimize delays and improve overall performance.

Integration of Peripherals:

  • Integrate commonly used peripherals (timers, counters, I/O ports) with a flexible and easy-to-use interface.

Example Instruction Set Enhancements:

  • Extended Arithmetic: Combine Z80’s complex arithmetic operations (e.g., multiplication, division) with 6502’s efficient basic operations.
  • Block Operations: Implement Z80’s block move and block search instructions.
  • Bit Manipulation: Include advanced bit manipulation instructions from the Z80.

By merging these features, the new hybrid CPU would aim to offer the power and flexibility of the Z80, with the simplicity and efficiency of the 6502, creating a versatile and powerful processor suitable for a wide range of applications. This conceptual design would provide both high performance and ease of use, appealing to developers familiar with either of the original processors."

==//==

Since this forum have a great number of experts on both processors, I decided to share this weird conversation I had with a machine.

What do you guys think of the suggested hybrid?

I continued this “what if” scenario by asking how could we improve our hybrid CPU by implementing more modern features, and which features would be more easily implemented. I think we reached a cool result in the end.

If anyone wish to know which features it suggested we should implement, just ask! :grin:

I allways thought the ultimate 8 bit cpu, was the Hitachi 6309.
The Japanese may have also had a better Z80 at one time.
http://elm-chan.org/docs/dev/kl5c8012_e.html

4 Likes

The good news: bit instructions are already implemented in the WDC 65C02S, the flavor of 6502 currently available. (So, ChatGPT may require an update, here.)

The bad news: I don’t think that the complexity of CISC instructions and the simplicity of the 6502 would go hand in hand well. Implementing block move would probably involve adding considerable circuitry. The same goes for complex arithmetic: the 6502 really just can add with carry (even SBC is just ADC with 1’s complement of the operand, adding a simple inverter, and 2s’ complement is achieved by the addition of the carry). Multiplication and division, even in their most atomic form as shift steps, require at least one double-length register. Any complex operations require some sort of sub-timing network and probably additional internal registers for managing sequences. – In other words, the “philosophical gap” is just too wide.

(Regarding this “philosophical gap”: The Z80 owes much to the Intel 8008, which is in turn really the processor of the Datapoint 2200, which was built around a serial shift register for memory, with sequential access. Hence, the philosophy here is that as much as possible should be done in the processor, since memory and its access is slow and expensive. The 6502, on the other hand, as a descendant of the 6800, is dramatically the other way round, building on the fact that random access memory had been becoming faster and faster and come down in price, which allows to put less and less into the CPU, which may thus be reduced in complexity – and price! – quite a lot, which is facilitated in turn by the fact that simple operations are also fast. Not enough internal registers? Just use the zero-page for a lot of slow(er) registers! If, however, we were to force the 6502 to do more complex things, thus adding to its inner complexity and pipeline, the whole concept collapses. – Crucially, I don’t think that we may expect a LLM to grasp such implications.)

Regarding pipelines, a look at C machines and their CRSIP architecture may be worth it, which internally transforms variable length instructions into fixed length for rapid execution by the help of a prefetch buffer and an instruction cache. But, while this allows the execution unit to consist just of a 3-stage pipeline, the initial decoding pipeline is already 3 stages, close the the average cycle count of a 6502 instruction. This only pays off, if we have multiple pipelines in parallel and can interleave (and cache) those two stages. Which is, again, far from the simplicity of the 6502.

I’d rather suggest to venture into the other direction: transforming the 6502 into a fixed-length, single instruction-word architecture, with a 24-bit word length (8 bit instruction part, 16-bit address/operand). Memory has become cheap and transistor count on the chip isn’t that much of an issue, anymore. Even, if this implies going 16-bit in register length. Also, a barrel or serial shifter, please, allowing for shifts and rotates by up to 8 bits in a single instruction.
Pretty much a PDP-1 with a stack and an additional Y-register, but without the universal indirection feature. As any word includes already an address part, we could apply any of the traditional zero-page modes to any address, thus making up for the universal indirection. Speaking of the PDP-1, division and multiplication shifts would be nice to have, and, if we were adventurous, automating them over the entire 16-bit operand length by the use a sub-timing chain. But this could be left to a more expensive variant. – Notably, in mid-1970s terms, this would probably bring us closer to the $1,000 range than the $24, and may not be considered as being in the “true spirit”, anymore. Also this would mean to have all 16-bit interface chips and 24-bit bus boards, which was pretty much out of scope at the time.
(I think, Apple had once an internal project for a fixed-length RISC 6502. But I don’t know any details of that architecture.)

1 Like

I am playing around with 20 bit cpu’s ( more once I get over this summer cold )
as it keeps things simple, and gives a good address range. Anything bigger
gets you into 24,32,36 bit machines and out the home brew era of the 1970’s.
Hal Chamberlin had a 16 bit home brew computer in the early 1970’s

 The wye 20 is a medium speed, three phase digital computer using LS TTL 
parts with a a word width of 20 bits and a byte with of 10 bits. 9 digit
binary floating point.4K dynamic ram or 1.8 uS core memory provide the base 48Kb of memory
with 32kb ram and ROM/CORE for bootstrap and other operating system 
routines.
Emulation of the CPU, will use later PAL and bitslice parts.

Cpu model:

The cpu has a Carry flag and 4 general purpose registers A,B,C,D and 3
index registers S X Y and instruction pointer Z (zero).
Index registers do not affect the carry.

Adressing modes are register indirect:
            +r -r r% r+ r-
indexed:    r n
immediate:  # n

opcode postfix  .   byte
                %   register

Instruction format:


  modes:
  0     nop and shift

        nop
     5    4    3    2    1    
  +----+----+----+----+----+
  |0000| AAA|  0 |    :    | 
  +----+----+----+----+----+

        shift ac

     5    4    3    2    1    
  +----+----+----+----+----+
  |SSSS| AAA|  0 |    :    | NORMAL
  +----+----+----+----+----+

  1     set condition
        if ac condtion is true set ac to constant
        else set false (0)

     5    4    3    2    1    
  +----+----+----+----+----+
  |NCCC| AAA|  1 |    :+###| 
  +----+----+----+----+----+

 2     memory ref reg indirect
    (EFA)= AAA  (STORE)
    AAA  = AAA OP (EFA) 
  

     5    4    3    2    1    
  +----+----+----+----+----+
  |COOO|PAAA|  2 |BXXX:+###| 
  +----+----+----+----+----+
    P PRE ADDITION
    B BYTE

 3     memory ref INDEXED
    (EFA)= AAA  (STORE)
    AAA  = AAA OP (EFA) 
  
     5    4    3    2    1    
  +----+----+----+----+----+
  |COOO| AAA|  3 |BXXX|    | 
  +----+----+----+----+----+
  |####|####|####|####|####| 
  +----+----+----+----+----+
    
 4    jump to subroutine
      memory ref BYTE imediate

      JSR register indirect
      T = (efa)
      (--S)= Z,Z=T
 
     5    4    3    2    1    
  +----+----+----+----+----+
  |0000|PAAA|  4 | XXX|+###| 
  +----+----+----+----+----+
    P PRE ADDITION

    memory ref BYTE imediate
    AAA = AAA OP #
     5    4    3    2    1    
  +----+----+----+----+----+
  |COOO| AAA|  4 |+###|####| 
  +----+----+----+----+----+
    
    
 5   lea and control
     lea
 
     5    4    3    2    1    
  +----+----+----+----+----+
  |0000| AAA|  5 | XXX|    | 
  +----+----+----+----+----+
  |####|####|####|####|####| 
  +----+----+----+----+----+
    control
     5    4    3    2    1    
  +----+----+----+----+----+
  |ffff|    |  5 |    |    | 
  +----+----+----+----+----+

     5    4    3    2    1    
  +----+----+----+----+----+
  |0001|    |  5 |    |    |  HALT
  +----+----+----+----+----+

 6   jump on condition
     register indirect
 
     5    4    3    2    1    
  +----+----+----+----+----+
  |NCCC|PAAA|  6 | XXX|+###| 
  +----+----+----+----+----+

      
 7   jump and register operate
     jmp indexed
 
     5    4    3    2    1    
  +----+----+----+----+----+
  |0000| AAA|  7 | XXX|    | 
  +----+----+----+----+----+
  |####|####|####|####|####| 
  +----+----+----+----+----+
    
     reg operate
     AAA = AAA OP XXX

     5    4    3    2    1    
  +----+----+----+----+----+
  |COOO| AAA|  7 | XXX|    | 
  +----+----+----+----+----+
 
OPCODE TABLES:
     REGISTER

          AAA   XXX       
     0    A     A         
     1    B     B
     2    C     C
     3    D     D
     4    S     S
     5    X     X
     6    Y     Y
     7    Z(PC) Z(ZERO) OR #

     MEMORY REF

     OOO  OP       
     0    ST    (EFA) = AAA            
     1    ADD/C  AAA  = AAA +  (EFA) + ?0,C
     2    SUB/C  AAA  = AAA + ~(EFA) + ?1,C
     3    CAD/C  AAA  = ~AAA + (EFA) + ?1,C
     4    LD     AAA  = (EFA)
     5    OR     AAA  = AAA |  (EFA)
     6    AND    AAA  = AAA &  (EFA)
     7    XOR    AAA  = AAA ^  (EFA)

    SHIFT 
    LATER
    
    LOGIC CC
    LATER


Several 4 bit slice designs, to speed up the 8080 came out using 2901 bit slice and other high speed parts. Perhaps they can be adapted to give 24 bit addressing on the 8080 and more z80 like functions.

The AI probably focused on the basic, original 6502 since it was what I requested, but as another exercise, we could for instance see what ChatGPT can do regarding the 65C02S, can it be improved, how it compares with newer Z80s like the eZ80, and so on…

While my knowledge on this subject is EXTREMELY basic compared to you guys, I kinda reached the same conclusion about the whole “philosophical gap”. From my point of view - and bear in mind I am no expert, just an enthusiast - It seemed by the end of the exercise that the 6502 didn’t add much to the Z80 and vice-versa.

Your answer kinda confirmed my suspicions, and although I quite don’t understand the topic with such depth that you clearly do… The point was made that they were conceptually different and built with opposite approaches toward RAM and that kinda defeat the effort of merging them.

Regarding your suggestion, of transforming the 6502 into a fixed-length, single instruction-word architecture, I would love if you could elaborate more. What would be the gains of such endeavor? Was that the direction WDC went with the 65C02S and the 65C816?

Thank you again for sharing your knowledge.

BTW ideas about improving 6502 have come up many times before on the 6502 forum - I created an index thread:

2 Likes

Interesting, I never heard of 20-bit CPU but kinda got the feeling, from previous exercise, that indeed going into 24-bit or higher gets you out of the spirit of those old wonders like the Intel 8080, Motorola 6800, MOS 6502 and Zilog Z80.

If we were to make a 20-bit 6502, how would be its performance compared to the more modern iterations it went like the 65C02? Which new features would it end up having (or that would be feasible/possible to implement)? Can you tell me more about it? I thank you kindly for your answer.

Also, I knew the japanese were into cloning Z80s and 6502s, but never knew they improved upon it. Will definitely look into it.

Thank you, this will be an interesting study. Can I ask you a question? Ever since I joined I see much love for the 6502 and its successors from WDC, but I don’t see many people discussing the Z80 and its family. Am I wrong and this is just a superficial impression or indeed the 6502 has more “fans”?

If so, why?

It might be true that in this forum 6502 looms larger - both myself and @NoLand are 6502 fans. No issues with z80 topics, of course. It’s been noted over on the 6502.org forum that there doesn’t seem to be a comparable z80 forum - that might be true, or it might be ignorance!

It might be that z80 being more complex (it’s four times the size) has something to do with it.

We have, presently, 67 z80 topics here, and 95 mos6502 topics - but not all topics are tagged, so that will be an undercount in both cases.

2 Likes

That makes much sense! By being simpler the 6502 seems to be more “ideal” for retro computing homebrew… :thinking:

I didn’t found anything of the sort regarding the Z80 on the internet, this type of discussions on improvements and such.

What about you EdS, how would you improve the 6502? Are you happy with the direction the WDC went with its family?

While this admittedly true, Z80 was actually the first instruction set, I’ve ever learned (and also the only one, I was ever taught), but I haven’t used it much. (There’s still a Sharp MZ-80K waiting to be thoroughly explored, though.) There are times, where I whish for more internal registers on the 6502, and I may miss some of the features of the PDP-1 (see above), which may be my absolute favorite instruction set (at least, there is a certain charm to this). But, you get what you get, and I’m fine with that, especially, since I can see the reasons for this. – And the fun is really in the restrictions! :slight_smile:

Regarding Z80 related fora, I’m mostly ignorant, but there are certainly dedicated homebrew communities, as well (esp. for the “Speccy”).
A decisive factor may be that many of the best selling 6502 home computers, like the Atari 8-bits including the VCS/2600 and Commodore 8-bits, were popular around the world, while popular Z80 machines seem to have been homed mostly in the UK and Japan and often weren’t available in the US.

1 Like

Me too - although I’m just another user/contributor here…

Back in the late 70s/early 80s there was of-course the great 8-bit CPU wars with most either being in the 6502 or Z80 camp. Very probably due to the cost of the systems available at the time - The good, well featured 6502 systems - Apple II, BBC Micro, OSI/Computkit/UK101, AIM-65, Oric-1 and many others but on the Z80 front there was the S100 systems - not really aimed at home use, but then the cheaper Sinclair range - ZX-80, 81, Spectrum, and latterly the Amstrad range, then MSX (but not until about '83). Some might say barely usable in the early days, but they did get better…

So maybe it’s an age thing.

I did some 8080 assembly (actually, a lot for the time) but using a Z80 syntax assembler on a Z80 CP/M system (I downloaded the code into the 8080 system) but that was that - early 80s. I’ve not touched a Z80 since.

I have used a combined 6502/z80 system - the Cerberus 2080 thing… It’s an interesting curiosity if nothing else - I can’t see a real practical use for it other than as a nice curiosity. The CPUs are mutually exclusive too - it’s one or the other in the same memory system.

But one hybrid 6502/Z80 CPU? Personally, no. The 65816 has some nice features like block-move and 16-bit reisters, but I’m not convinced it’s that better. Might as well start from fresh…

-Gordon

I can’t answer for Ed, but can give you some of my own thoughts, having designed and built an SBC featuring the WDC successor to the W65C02 - the W65C816… (And also written a lot of code for it)

Am I happy with the way they went? No, not really. Various stories suggest the '816 was influenced by Apple and what they wanted at the time (a degree of Apple II compatibility, maybe?) - it seemed to be late to the market and not as fast as it could have been (in the early days at least) It’s also awkward to write efficient code for - especially if you want to deal with data sets over 64KB in size - which arguably might not be something you should be doing with such a device, but at the time (mid 80) people were already building large spreadsheets (Visicalc) and word processing on systems with 128KB and more RAM so looking for easier ways to handle large data. So it’s not just a 16-bit 6502, but a new CPU that needs new programming models, tip and tricks for.

ARM is considered by some to be the successor to the 6502 and I sort of have to agree there - but I may be biased, having just migrated my existing '816 project over to ARM and finding it a joy to write (assembly) code for compared to assembly on the '816.

With the 6502 you know its limitations - but the '816 - it seemed to promise much more but didn’t (in my mind) really deliver.

-Gordon

2 Likes

I’d second that. The 6502 was born from a certain situation and its needs — and was great for this, but further developments, addressing more powerful hardware, mostly failed.

The 6502 is probably the more enjoyable, the more restricted the system. E.g., a few weeks ago, I wrote a game for the Commodore PET (it’s still lacking sound, or what the PET has instead of this :slight_smile: ) and really enjoyed it. Writing a spreadsheet for the Apple IIGS may be another story.

2 Likes

Somebody already built a processor combining the 6502 and the Z80:

Isetta TTL Computer

2 Likes

Well, I’m not impressed by the '816, although it has its merits. I think modes are a bad idea, at least for data widths (decimal mode isn’t really a problem.) I would imagine using distinct opcodes, or a prefix byte, or suffix bytes, would all be better.

Having said which, my quick look at the Agon Light tells me that the eZ80 is a well-done backward-compatible expansion of the Z80.

Which reminds me, the RC2014 and the retrobrewcomputers forum and wiki are one place where z80 enthusiasts interact.

As for improving the 6502, one thing I did do was a very rough and ready and completely incompatible rework called the 65Org16

And another thing I had a small hand in, not entirely unadjacent to the 6502, was the OPC series of projects.

In both cases, the desire was to make something which worked and was simple. That’s not (in my view) about collecting ideas for features, or filling up an opcode matrix, but about seeing what the internal architecture looks like to make a useful CPU that’s interesting to program.

In both cases, there was no thought of compatibility. Of course, most people thinking of extensions or expansions are thinking of compatibility, usually with some specific family of retrocomputers, and sometimes stuck in the predicament of needing to replicate undocumented behaviour as well as the datasheet spec.

1 Like

Ever since I joined I see much love for the 6502 and its successors from WDC, but I don’t see many people discussing the Z80 and its family.

Hehe, that’s funny because I got the opposite impression. Personally? I love the 6502, mainly because of the C64. But coding on it … I absolutely love its goofiness compared to a CPU that makes sense, but I can’t really point to anything about it which is “superior” beyond it being less costly at a specific time when that difference in cost mattered.

I think that a CPU which combined the best features of the Z80 and 6502 would be … a Z80.

And this is from someone who has zero interest in coding anything Z80.

1 Like

Oh, you remind me, I wrote something up not too long ago:

3 Likes

They could all be closet apple ][ fans, rather than just for the 6502. :slight_smile:
The 6502 is a single chip micro-computer, as the 6800 and 8080 required
more support chips and often voltages other 5 volts. This leads to simple computer design with a cpu, i/o some rom and ram, something anybody can
understand.

The z80 is more complex than the 8080, but for the most part just was used as
faster 8080.

1 Like

Z80 and 6502 communities are ‘tribal’, the more current term maybe ‘echo chamber’. 6502 groups do not talk about Z80; and Z80 groups don’t talk about 6502. Retrobrewcomputers and Google’s RC2014 and retro-comp are mostly Z80. 6502.org is obviously 6502 only. Z80 is in fact more popular than 6502 as judged by hackaday entries and how many home brews are on eBay and Tindie.

I believe there are over 5000 RC2014 (Z80 based, designed in 2014) sold so far. There are likely just as many clones of RC2014 sold as well
Bill

3 Likes