Ben`s computer, pre- draft version 22-11-26
Octal 77 is a simple 32 bit computer using MSI and LSI logic from 1977, using a
16 bit bus with up to 20 bits of address space. The bus speed about 1.5 mhz, for
a 80 x 25 Video Card (25Mhz). Two 2400 baud serial ports and two emulated 1.5
meg platter drives (SD cards) with 8 Kb BIOS and 96Kb ram are the standard sys-
tem. The octal front panel with Run/stop, adr/load, dep, exam, pc/ac,hi/low is
used to boot start the system.
Internaly 3 512 x 8 proms are for the microcode. 2901 bit slices are used for
the data path, on two 16 bit cards. Programable logic like the 82S100 may be
used for microcode decoding in 1977. A current version could use CMOS 22V10's
or just 74HCTXX. 100 ns flash proms would be the only programable parts then.
Altera`s DE1 Cyclone II, FPGA development system is used for prototyping the
TTL hardware.
* Internal memory model
32 16 8 1
+-----------------+--------+--------+
| | | | 6 GP registers A B C D X Y
+-----------------+--------+--------+
| | | | 4 GP optional registers E F G W .
+-----------------+--------+--------+ ± extended flag or sign
20 1
+------------+----+--------+--------+
|------------| . . | 2 special registers S PC
+------------+----+--------+--------+
[C] [R] [E] flags C carry R run E Enable IRQ
* OP CODE FORMAT
1 111 111
6 543 210 987 654 321
+-+---+---+---+---+---+
|-|000|AAA|.SS|MM.|XXX| MEM REF ST<SIZE> A <MODE> X (EFA)=AC
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|C|OOO|AAA|.SS|MM.|XXX| MEM REF OP<SIZE> A <MODE> X AC = AC OP (EFA)
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|-|000|AAA|.00|000|###| CTL CONTROL = NOP,HLT,DI,EI
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|-|000|AAA|.00|01±|###| JSV A Z (-S) = PC, PC = #ADR
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|0|000|AAA|.00|10.|XXX| LEA A X # AC = EFA
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|0|000|AAA|.00|11±|###| LEA A Z AC = #ADR
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|C|OOO|AAA|.00|01.|XXX| OP$ A X AC = AC OP IX (EXCESS 3)
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|C|OOO|AAA|.00|10±|###| QUICK # AC = AC OP # QUICK
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|I|CCC|AAA|.00|11±|###| BCC A # IF(CC) PC = #ADR
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|-|SSS|AAA|.01|00#|###| SFT A # SFT AC #N TIMES
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|-|111|AAA|.10|00.|XXX| JMP A R+ PC = (R+)
+-+---+---+---+---+---+
+-+---+---+---+---+---+
|-|111|AAA|.01|110|000| SCC A A = CONDITION(CC)
+-+---+---+---+---+---+
* FUNCTION MATRIX
A/X OP C COND SS MM SFT
+-----+--------+-------+-------+----+---+
0 |A E | ST - |- |REG %|-R |- |
+-----+--------+-------+-------+----+---+
1 |B F | - XOR|Z |BYTE . -R |SZL|
+-----+--------+-------+-------+----+---+
2 |C G | SBX BIT|S |SHORT :|R+,#|SCL|
+-----+--------+-------+-------+----+---+
3 |D W | ADX AND|S+Z |WORD |R+,#|ROL|
+-----+--------+-------+-------+----+---+
4 |X - | LD OR |~C |REG |R # |ROR|
+-----+--------+-------+-------+----+---+
5 |Y - | CAD CAC|~C+Z |BYTE |R # |SZR|
+-----+--------+-------+-------+----+---+
6 |S - | SUB SBC|1 |SHORT |Z |SCR|
+-----+--------+-------+-------+----+---+
7 |# - | ADD ADC|1 |WORD |Z |ASR|
+-----+--------+-------+-------+----+---+
* FRONT PANEL
+---+---+---+---+---+---+
| D | D | D | D | D | D | <run> NIXIE TUBES
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|PHS|SSS|SSS|SSS|SSS|SSS| D X A R PANEL AND FUNCTION SWITCHES
+---+---+---+---+---+---+
4 Likes
Moved JSV A Z to LEA A Z. Replaced the old JSV opcode, with BSV.
AC = PC + 2, PC += (PC+)
Used internaly for string literals.
Very interesting!
Octal programming, Nixie tubes, bit slice and 32 bits.
(I wonder why 32 bit).
How do you get this idea?
I’m looking forward reading more about it (and see a photo)
You mean turn back from the dark side, and use 36 bits.
The concept here is a simple 32 bit cpu would have 2 simple (slow)
alu cards and senseable 16 bit control section (24 bit wide microcode) compared to
the complex fast 2901 demo designs 8/16 bit designs out there.
A fast 8080 in bit slice.
bit slice demo design
For now sticking to the standard data sizes deems to be the safe bet
if I want to port any software over if I ever get C compiler, that will self port
in 128Kb.
The front panel is waiting for the XMAS elves to send the nixie tubes, so the panel
will not be built until January.
A 36 bit version could be built using 2901’s, but a FPGA version might not route,
so that design is paper only.
Ben.
1 Like
36 bits lives again, in the FPGA. The blinky lights blink.
I now just have 256 Kb total static ram memory on the FPGA. That seems to be so small
for a 36 bit cpu, with 9 bit bytes.
The TTL version will use 5 2901’s on the first card, and
4 2901’s on the second for 36 bits.
Now I need to clean up my software for 36 bits using long longs.
Ben.
1 Like
Ben's computer, 36 bit draft version 22-02-12
Octal 36 is a simple 36 bit computer using MSI and LSI logic from 1977,using a
18 bit bus with up to 20 bits of address space.The bus speed about 1.5 mhz, for
a 80 x 25 Video Card (25Mhz). Two 2400 baud serial ports and two emulated 1.5
meg platter drives (SD cards) with 8 Kb BIOS and 96Kb ram are the standard sys-
tem. The octal front panel with Run/stop, adr/load, dep, exam, pc/ac,hi/low is
used to boot start the system.
Internaly 3 512 x 8 proms are for the microcode. 2901 bit slices are used for
the data path, on 2 20/16 bit cards. Programable logic like the 82S100 may be
used for microcode decoding in 1977. A current version could use CMOS 22V10's
or just 74HCTXX. 100 ns flash proms would be the only programable parts then.
Altera's DE1 Cyclone II, FPGA development system is used for prototyping the
TTL hardware. 256Kb or 64K words total memory. 16K words is reserved for OS.
* Internal memory model
36 18 9 1
+-----------------+--------+--------+
| | | | 6 GP registers A B C D X Y
+-----------------+--------+--------+
| | | | 4 GP optional registers E F G W .
+-----------------+--------+--------+ ± extended flag or sign
20 1
+------------+----+--------+--------+
|------------| . . | 2 special registers S PC
+------------+----+--------+--------+
[C] [R] [E] flags C carry R run E Enable IRQ
* OP CODE FORMAT
111 111 111
876 543 210 987 654 321
+---+---+---+---+---+---+
|0a-|000|AAA|.SS|110|0±#| DIRECT 20 bits
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0a-|000|AAA|.SS|MMx|XXX| MEM REF ST<SIZE> A <MODE> X (EFA)=AC
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0aC|OOO|AAA|.SS|MMx|XXX| MEM REF OP<SIZE> A <MODE> X AC = AC OP (EFA)
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|00-|000|AAA|.00|000|###| CTL CONTROL = NOP,HLT,DI,EI
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0a-|000|AAA|.00|010|000| LIT interal use
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0a0|000|AAA|.00|10x|XXX| LEA A X # AC = EFA
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0a0|000|AAA|.00|110|0±#| JSV A Z (-S) = PC, PC = #ADR
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0aC|OOO|AAA|.00|01.|XXX| OP$ A X AC = AC OP IX (EXCESS 3)
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0aC|OOO|AAA|.00|10?|###| QUICK # normal AC = AC OP # QUICK
+---+---+---+---+---+---+ or JAMMED extended
+---+---+---+---+---+---+
|1aC|OOO|AAA|±##|###|###| QUICK # extended AC = AC OP # QUICK
+---+---+---+---+---+---+ reserved
+---+---+---+---+---+---+
|0aI|CCC|AAA|.00|11?|###| BCC A # IF(CC) PC = #ADR
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0a-|SSS|AAA|.01|00#|###| SFT A # SFT AC #N TIMES
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0a-|111|AAA|.10|00.|XXX| JMP A R+ PC = (R+)
+---+---+---+---+---+---+
+---+---+---+---+---+---+
|0a-|111|AAA|.01|110|000| SCC A A = CONDITION(CC)
+---+---+---+---+---+---+
* FUNCTION MATRIX
A/X OP C COND SS MM SFT
+-----+--------+-------+-------+----+---+
0 |A E | ST - |- |REG %|-R |- |
+-----+--------+-------+-------+----+---+
1 |B F | - XOR|Z |BYTE . -R |SZL|
+-----+--------+-------+-------+----+---+
2 |C G | SBX BIT|S |SHORT :|R+,#|SCL|
+-----+--------+-------+-------+----+---+
3 |D W | ADX AND|S+Z |WORD |R+,#|ROL|
+-----+--------+-------+-------+----+---+
4 |X - | LD OR |~C |REG |R # |ROR|
+-----+--------+-------+-------+----+---+
5 |Y - | CAD CAC|~C+Z |BYTE |R # |SZR|
+-----+--------+-------+-------+----+---+
6 |S - | SUB SBC|1 |SHORT |Z |SCR|
+-----+--------+-------+-------+----+---+
7 |# - | ADD ADC|1 |WORD |Z |ASR|
+-----+--------+-------+-------+----+---+
* FRONT PANEL
+---+---+---+---+---+---+
| D | D | D | D | D | D | <run> NIXIE TUBES
+---+---+---+---+---+---+
+---+---+---+---+---+---+
PP|SSS|SSS|SSS|SSS|SSS|SSS| D X A R PANEL AND FUNCTION SWITCHES
+---+---+---+---+---+---+
1 Like
On the Honeywell L66 C code used to mostly work with 9bit char, 18bit short 36bit long so I am not sure it’s a big challenge for most code. Stuff that does arbitrary precision maths isn’t always so pretty.
The compiler I’ve been working on (had a bit of halt because of real life) fits in 48K on Z80 if built with SDCC. I’ve got bugs to chase out to get it generating correct 8085 for all cases, but once that is done I want try and get it self hosting and then sort some other targets out.
It’ll have fits with 36bits but that should easily be fixable if you get this thing up and working (just needs some typedef and “32bit is enough” assumptions fixing up, plus probably pointer casting rules). It’s default behaviour is to output a lot of subroutine calls and then you teach the backend the bits your processor can do directly.
It is the macro processer that C uses that keeps me from writing a C compiler.
For all intents C is a 16 bit compiler, that has been hacked to 32 and 64 bits.
If a C compiler supports long, it would be no problem to port providing you a had sane
intermedate language.
I like the idea of non 32 bit computer, because then you can have realistic single word floating point number. Can you add 999,999.99 + .01 to give $1,000,000,00?
I am toying with the idea, of a 22 bit computer, that will give 9 decimal places in BCD.
Bytes are 11 bits unsigned. 7 bit ascii strings could be packed 3 per word.
Can the octal front panel fit, (7 digits , ± tube) fit using nixie tubes?
Ben.
The problem is bootstrapping it. It’ll work on a 64bit system I think because long is 64bit and then if it ever got self hosting that would work on 36bit as it would have 36 bit longs.
There are a bunch of C preprocessor implementations that can be repurposed trivially. Right now I’m just abusing the gcc one but will switch to something small when I’ve got time to tweak the DECUS one a bit or look at a couple of others.
Boot strapping would be done on a 32 bit cpu. I have up to 128Kb of ram for that.
Since bytes,shorts and longs are hardware sizes, I only have to make a few minor
changes between different cpu widths. Most are just only in my bios routines,
for size dependant items; loop n times, where n is word size.
Update. I got test version of a 12/24/48 bit cpu working. I may develop this after I test a few
more things. The major advantage is I have 11 digit single word binary floating point, over
a 32 or 36 bit cpu. The main disadvantage I need a new the front panel. A 12 " x 6 " PCB, I expect. Ben.
It’d be great to see photos of a home-built front panel, when the time comes!