Reposted with permission - from [Jaut-76 M7BLJ]over on the stardot discord, a front panel thought to be Ferranti-associated. My own speculation is that it might have to do with the F100-M, which was the discrete chip version of the F100-L integrated circuit, and that’s because of the need to twiddle with internals, easy enough in one case and not easy in the other case.
top row is labelled ‘highway’ and has 8+12 lamps, and 7+12 switches. They are grouped in sets of four. From the right, the first 15 are labelled with powers of two from 2⁰ at the right up to 2¹⁴. From the left, the first lamp is labelled ‘gen res’ and has no switch. The next four lamps have switches and are labelled ‘ser req’, ‘dev strobe’, ‘store strobe’ and ‘write’.
bottom row, from the left, a group of 4 lamps and switches labelled Scratch Pad Address and with powers of two
towards the middle of the bottom row, a group of three. Two yellow switches without lamps, labelled ‘inhib ctrl’ and ‘gen res’, then a three-position red switch with lamp labelled ‘stop’, the switch labelled with ‘micro step’, ‘inst stop’ and ‘go’
to the right of those another group of three switches, above them a group of 6 lamps labelled with ‘microstep address’ and with powers of two. The first switch is white, labelled ‘load P’, then a blue one labelled ‘load SP’ and then a black one labelled ‘load I’
finally at bottom right a green switch labelled START.
Here’s the back - little circuit boards with (presumably) driver transistors, lots of wires, and two big connectors labelled F101 and F102:
The results of two years work on this development in the field of computer-aided measurement are described. The evolution of the concept, experience of building a prototype with the F100-M processor and present work on the hardware and software of fully developed systems based on the F100-L microprocessor are covered.
The idea here is a small portable signal acquisition computer which can be moved and docked with a more powerful computer after the measurements.
A long term aim of this research is to develop a portable device, which could, for example, be carried on the person of a patient undergoing continuous monitoring. Hence, size, weight and power consumption are important factors in the choice of technology.
Note also:
We were fortunate to have early access to information on the proposed F100-L device which exhibits many of these features although it has no internal multiply/divide and only one internal register. This was’. used in the development work to replace the F100-M in the first processor that was built using the medium scale integration (MSI) form.
…
The F100-M prototype was begun 18 months before the F100-L processor and its important interface chips were available. In this computer the equivalent of the F100-L chip is a five board MSI processor and I/O is handled by a two board controller. The processor is functionally identical to the large scale integration (LSI) version, but the controller is not as effective as the LSI interface set, which has led to some problems.
Edit: this looks like the F100-M version opened up:
Do we know if Scratch Pad means the same as in Texas Instruments terms, i.e. a base address of switchable registers for multi-user/task operations?
(Meaning, was this a generally established term, or is this rather a term quite natural to come up with for any kind of a temporary store with a variety of applications?)
The TMS9900, known from the TI-99/4(A) has a 256 bytes workspace memory mapped to RAM, which are contain the CPU registers. A Workspace Pointer controls the base address of the register block currently in use, allowing for fast contex switching. On the TI-99/4(A), this special memory area is known as “scratchpad RAM”.
I thought, the term scratchpad must have propagated from the TI-990 mini, which provided the architectural blueprint for the TMS9900, but I can’t find any evidence for this. – Which kind of answers my question, already.
Thanks. I got briefly excited when I found that Ferranti did a kind of MMU which allowed 6 banks of RAM - or more banks if decoded. But I don’t think it’s a fit. Also, it’s for the F200, which is broadly compatible AFAICT but not the same chip:
F200 memory can be organised as a page system with one base page and up to 31 other pages, each consisting of a 32K memory block. F220-L is connected to each of these memory pages via page enable lines. In a simple configuration F220-L will access the base page and five other pages. F220-L can access all 32 pages, to give a total one megaword, when external decode logic is added to the system. F220-L can also provide paged addressing for up to 6 input/output modules in the system, which interface to the Memory Paging Controller via the DMA daisy chain. The ability of F220-L to handle memory requests from both the F200-L and input/output peripherals is a significant advantage to the designer, greatly simplifying the configuration of sophisticated real-time systems.
I noticed that Ferranti’s marketing materials mention a Highway - distinguishing, I think, a demultiplexed bus suitable for memory from the CPU’s multiplexed bus, which they call the I/O bus.
The F100-L uses a data and address multiplexed input/output bus, over which F100-L handles all memory and peripheral devices.
To enable memory and peripheral devices to be connected to the I/O Bus in a simple, modular fashion, Ferranti have developed further LSI devices known as the Interface Set.
An Interface Set comprises three LSI chips, of two types:-
F111-L, Control Interface Chip 1 off
F112-L, Data Interface Chip 2 off
Here’s Ferranti’s own dev system for the F100-L - it uses a handset, not a front panel.
The concept of a control handset is interesting – and it’s new to me.
From the Hardware Data Book:
The optional Control Handset includes a ROM bootstrap to enable
programs to be entered into RAM in a simple, straightforward manner.
Facilities for manually entering data into memory are also provided.
The Control Handset interfaces to the system via the I/O Bus with
additional signals going direct to the processor.
and
The Control Handset contains control keys (e.g. Run, Reset) an octal
number entry keyboard, and a 6 digit LED display.
The facilities can be summarised as follows:
(a) Normal control of the running of the program using the
Reset, Run and Single Step keys
(b) In the Stop condition, loading of information from the
keyboard into the PC or memory.
(c) Monitoring the current value of PC, the Instruction
Register or a memory location.
(d) Program load from an I/0 device, using the keyboard to
define the particular I/O device being used, and the ROM
Loader on the Interface card.
(e) System state monitoring (e.g. Stop, Fail).
Historical footnote: Maybe a forerunner of this was the control panel of the BBN PDP-1 prototype (which became Ed Fredkin’s timesharing system). While not in handset format, the hexagonal console was a separate device to be put on a desk, etc. As was the paper tape reader, so the principal operational and control units were separate from the cabinet.
The TMS9900 has 16 virtual registers which are actually 32 bytes in memory pointed to by the workspace register. The can be located anywhere in the 64KB address space, but the basic TI99/4A only had 256 bytes of RAM you could use this way. Since any RAM expansion would only be 8 bits wide pointing W there would slow down the processor quite a bit, but it should work.
